Show patches with: Submitter = Nelson Chu       |    State = Action Required       |    Archived = No       |   138 patches
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Patch Series S/W/F Date Submitter Delegate State
RISC-V: Support svinval extension. RISC-V: Support svinval extension. 0 0 0 2021-07-22 Nelson Chu New
[committed] RISC-V: Minor updates for architecture parser. [committed] RISC-V: Minor updates for architecture parser. 0 0 0 2021-07-20 Nelson Chu New
[v4] RISC-V: Extend .insn directive to support hardcode encoding. [v4] RISC-V: Extend .insn directive to support hardcode encoding. 0 0 0 2021-07-16 Nelson Chu New
[v3,2/2] RISC-V: Extend .insn directive to support hardcode encoding. RISC-V: The series to supporting mapping symbols. 0 0 0 2021-07-13 Nelson Chu New
[v3,1/2] RISC-V: PR27916, Support mapping symbols. RISC-V: The series to supporting mapping symbols. 0 0 0 2021-07-13 Nelson Chu New
[v2,1/3] RISC-V: Enable elf attributes when default configure option isn't set. [v2,1/3] RISC-V: Enable elf attributes when default configure option isn't set. 0 0 0 2021-07-09 Nelson Chu New
[v2] RISC-V: Clarify the addends of pc-relative access. [v2] RISC-V: Clarify the addends of pc-relative access. 0 0 0 2021-06-22 Nelson Chu New
[integration,4/4] RISC-V/rvv: Removed Zvamo from standard v, and then changed version to 1.0. RISC-V/rvv: Update rvv from v01.0 to v1.0 except zve feature. 0 0 0 2021-06-21 Nelson Chu New
[integration,3/4] RISC-V/rvv: Changed assembler mnemonic for unordered floating-point reductions. RISC-V/rvv: Update rvv from v01.0 to v1.0 except zve feature. 0 0 0 2021-06-21 Nelson Chu New
[integration,2/4] RISC-V/rvv: Changed assembler mnemonic for mask loads/stores. RISC-V/rvv: Update rvv from v01.0 to v1.0 except zve feature. 0 0 0 2021-06-21 Nelson Chu New
[integration,1/4] RISC-V/rvv: Added assembly pseudoinstructions, vfabs.v. RISC-V/rvv: Update rvv from v01.0 to v1.0 except zve feature. 0 0 0 2021-06-21 Nelson Chu New
[committed] RISC-V: Update the riscv_opts.[rvc|rve] in the riscv_set_arch. [committed] RISC-V: Update the riscv_opts.[rvc|rve] in the riscv_set_arch. 0 0 0 2021-06-11 Nelson Chu New
RISC-V: Reorder the prefixed extensions which are out of order. RISC-V: Reorder the prefixed extensions which are out of order. 0 0 0 2021-05-31 Nelson Chu New
[RFC] RISC-V: PR27916, Support mapping symbols. [RFC] RISC-V: PR27916, Support mapping symbols. 0 0 0 2021-05-29 Nelson Chu New
[committed] RISC-V: Allow to link the objects with unknown prefixed extensions. [committed] RISC-V: Allow to link the objects with unknown prefixed extensions. 0 0 0 2021-05-26 Nelson Chu New
RISC-V: PR25212, Report errors for invalid march and mabi combinations. RISC-V: PR25212, Report errors for invalid march and mabi combinations. 0 0 0 2021-05-21 Nelson Chu New
[2/2] RISC-V: PR27180, update changed relocations when relocating, for --emit-relocs. [1/2] RISC-V: Clarify the addends of pc-relative access. 0 0 0 2021-05-20 Nelson Chu New
[1/2] RISC-V: Clarify the addends of pc-relative access. [1/2] RISC-V: Clarify the addends of pc-relative access. 0 0 0 2021-05-20 Nelson Chu New
[committed] RISC-V: Check the overflow for %pcrel_lo addend more strictly. [committed] RISC-V: Check the overflow for %pcrel_lo addend more strictly. 0 0 0 2021-05-14 Nelson Chu New
[committed] RISC-V: Record implicit subsets in a table, to avoid repeated codes. [committed] RISC-V: Record implicit subsets in a table, to avoid repeated codes. 0 0 0 2021-05-13 Nelson Chu New
RISC-V: PR27566, Do not relax when data segment phase is exp_seg_relro_adjust. RISC-V: PR27566, Do not relax when data segment phase is exp_seg_relro_adjust. 0 0 0 2021-05-12 Nelson Chu New
[committed,integration] RISC-V/zfh: Added big endian testcase for .float16 directive. [committed,integration] RISC-V/zfh: Added big endian testcase for .float16 directive. 0 0 0 2021-05-10 Nelson Chu New
[committed] RISC-V: PR27436, make operand C> work the same as >. [committed] RISC-V: PR27436, make operand C> work the same as >. 0 0 0 2021-04-16 Nelson Chu New
[Integration,v2,4/4] RISC-V/zfh: Support .float16 directive for assembler. [Integration,v2,1/4] RISC-V/extended: Add assembler and dis-assembler hooks for extended extensions. 0 0 0 2021-04-15 Nelson Chu New
[Integration,v2,3/4] RISC-V/zfh: Add half-precision floating-point v0.1 instructions. [Integration,v2,1/4] RISC-V/extended: Add assembler and dis-assembler hooks for extended extensions. 0 0 0 2021-04-15 Nelson Chu New
[Integration,v2,1/4] RISC-V/extended: Add assembler and dis-assembler hooks for extended extensions. [Integration,v2,1/4] RISC-V/extended: Add assembler and dis-assembler hooks for extended extensions. 0 0 0 2021-04-15 Nelson Chu New
RISC-V: PR27584, surpress local and empty name symbols for nm. RISC-V: PR27584, surpress local and empty name symbols for nm. 0 0 0 2021-04-14 Nelson Chu New
[committed] RISC-V: Don't report the mismatched version warning for the implicit extensions. [committed] RISC-V: Don't report the mismatched version warning for the implicit extensions. 0 0 0 2021-04-13 Nelson Chu New
[committed] RISC-V: The version of i-ext should be RISCV_UNKNOWN_VERSION when expanding g-ext. [committed] RISC-V: The version of i-ext should be RISCV_UNKNOWN_VERSION when expanding g-ext. 0 0 0 2021-04-12 Nelson Chu New
[committed] RISC-V: Add i-ext as the implicit extension when e-ext is set. [committed] RISC-V: Add i-ext as the implicit extension when e-ext is set. 0 0 0 2021-04-12 Nelson Chu New
RISC-V: Support to parse the multi-letter prefix in the architecture string. RISC-V: Support to parse the multi-letter prefix in the architecture string. 0 0 0 2021-04-07 Nelson Chu New
[Integration,6/6] RISC-V/zfh: Support .float16 directive for assembler. RISC-V: The prototype of the integration and working branches for binutils. 0 0 0 2021-03-30 Nelson Chu Superseded
[Integration,5/6] RISC-V/zfh: Add half-precision floating-point v0.1 instructions. RISC-V: The prototype of the integration and working branches for binutils. 0 0 0 2021-03-30 Nelson Chu Superseded
[Integration,4/6] RISC-V/rvv: Add rvv v0.10 instructions. RISC-V: The prototype of the integration and working branches for binutils. 0 0 0 2021-03-30 Nelson Chu New
[Integration,3/6] RISC-V/sifive: Add sifive cache control instructions. RISC-V: The prototype of the integration and working branches for binutils. 0 0 0 2021-03-30 Nelson Chu New
[Integration,2/6] RISC-V/extended: Add assembler and dis-assembler hooks for extended extensions. RISC-V: The prototype of the integration and working branches for binutils. 0 0 0 2021-03-30 Nelson Chu Superseded
[Integration,1/6] RISC-V/extended: Add extended extension hooks when parsing architecture string. RISC-V: The prototype of the integration and working branches for binutils. 0 0 0 2021-03-30 Nelson Chu New
[committed,v2] RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling. [committed,v2] RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling. 0 0 0 2021-02-18 Nelson Chu New
[committed] RISC-V: PR27200, allow the first input non-ABI binary to be linked with any one. [committed] RISC-V: PR27200, allow the first input non-ABI binary to be linked with any one. 0 0 0 2021-02-17 Nelson Chu New
[committed,2/2] RISC-V: PR27348, Remove the obsolete OP_*CUSTOM_IMM. [committed,1/2] RISC-V: PR27348, Remove obsolete Xcustom support. 0 0 0 2021-02-05 Nelson Chu New
[committed,1/2] RISC-V: PR27348, Remove obsolete Xcustom support. [committed,1/2] RISC-V: PR27348, Remove obsolete Xcustom support. 0 0 0 2021-02-05 Nelson Chu New
[committed] RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions. [committed] RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions. 0 0 0 2021-02-04 Nelson Chu New
RISC-V: Add bfd/cpu-riscv.h to support all spec versions controling. RISC-V: Add bfd/cpu-riscv.h to support all spec versions controling. 0 0 0 2021-01-28 Nelson Chu Superseded
RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. 0 0 0 2021-01-27 Nelson Chu New
RISCV/ld: allow the first input non-ABI binary to be linked with any one. RISCV/ld: allow the first input non-ABI binary to be linked with any one. 0 0 0 2021-01-22 Nelson Chu New
RISC-V: Fixed the indent that caused by the previous commits accidentally. RISC-V: Fixed the indent that caused by the previous commits accidentally. 0 0 0 2021-01-15 Nelson Chu New
[3/3] RISC-V: Indent and GNU coding standards tidy, also aligned the code. [1/3] RISC-V: Comments tidy and improvement. 0 0 0 2021-01-15 Nelson Chu New
[2/3] RISC-V: Error and warning messages tidy. [1/3] RISC-V: Comments tidy and improvement. 0 0 0 2021-01-15 Nelson Chu New
[1/3] RISC-V: Comments tidy and improvement. [1/3] RISC-V: Comments tidy and improvement. 0 0 0 2021-01-15 Nelson Chu New
ld: Just xfail riscv little endian targets for compressed1d.d test. ld: Just xfail riscv little endian targets for compressed1d.d test. 0 0 0 2021-01-08 Nelson Chu New
[v3] RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93). [v3] RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93). 0 0 0 2021-01-07 Nelson Chu New
ld: xfail riscv64be-*-* for ld-scripts/empty-address-2 tests. ld: xfail riscv64be-*-* for ld-scripts/empty-address-2 tests. 0 0 0 2021-01-06 Nelson Chu New
[v2] RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93). [v2] RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93). 0 0 0 2021-01-05 Nelson Chu New
RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93). RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93). 0 0 0 2021-01-05 Nelson Chu Superseded
RISC-V: Fix the merged orders of Z* extension for linker. RISC-V: Fix the merged orders of Z* extension for linker. 0 0 0 2021-01-04 Nelson Chu New
RISC-V: Improve multiple relax passes problem. RISC-V: Improve multiple relax passes problem. 0 0 0 2020-12-18 Nelson Chu New
RISC-V: Ouput __global_pointer$ as dynamic symbol when generating dynamic PDE. RISC-V: Ouput __global_pointer$ as dynamic symbol when generating dynamic PDE. 0 0 0 2020-12-16 Nelson Chu New
[3/3] RISC-V: Add -menable-experimental-extensions option. RISC-V: Add -menable-experimental-extensions and support bitmanip instructions 0 0 0 2020-12-15 Nelson Chu New
[2/3] RISC-V: Define pseudo rev/orc/zip/unzip as alias instructions. RISC-V: Add -menable-experimental-extensions and support bitmanip instructions 0 0 0 2020-12-15 Nelson Chu New
[1/3] RISC-V: Support riscv bitmanip instructions. RISC-V: Add -menable-experimental-extensions and support bitmanip instructions 0 0 0 2020-12-15 Nelson Chu New
[v2] RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions. [v2] RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions. 0 0 0 2020-12-09 Nelson Chu New
RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions. RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions. 0 0 0 2020-12-09 Nelson Chu Superseded
RISC-V: Dump CSR according to the elf privileged spec attributes. RISC-V: Dump CSR according to the elf privileged spec attributes. 0 0 0 2020-12-08 Nelson Chu New
[v2] RISC-V: Control fence.i and csr instructions by zifencei and zicsr. [v2] RISC-V: Control fence.i and csr instructions by zifencei and zicsr. 0 0 0 2020-12-08 Nelson Chu New
RISC-V: Control fence.i and csr instructions by zifencei and zicsr. RISC-V: Control fence.i and csr instructions by zifencei and zicsr. 0 0 0 2020-12-03 Nelson Chu Superseded
RISC-V: Add DT_RISCV_GP dynamic tag to fix the uninitialized gp for ifunc. RISC-V: Add DT_RISCV_GP dynamic tag to fix the uninitialized gp for ifunc. 0 0 0 2020-12-01 Nelson Chu New
[8/8] RISC-V: Fix the order checking for Z* extension. RISC-V: Architecture string improvement 0 0 0 2020-11-27 Nelson Chu New
[7/8] RISC-V: Support to add implicit extensions for G. RISC-V: Architecture string improvement 0 0 0 2020-11-27 Nelson Chu New
[6/8] RISC-V: Support to add implicit extensions. RISC-V: Architecture string improvement 0 0 0 2020-11-27 Nelson Chu New
[5/8] RISC-V: Improve the version parsing for arch string. RISC-V: Architecture string improvement 0 0 0 2020-11-27 Nelson Chu New
[4/8] RISC-V: Remove the unimplemented extensions. RISC-V: Architecture string improvement 0 0 0 2020-11-27 Nelson Chu New
[3/8] RISC-V: Add zifencei and prefixed h class extensions. RISC-V: Architecture string improvement 0 0 0 2020-11-27 Nelson Chu New
[2/8] RISC-V: Don't allow any uppercase letter in the arch string. RISC-V: Architecture string improvement 0 0 0 2020-11-27 Nelson Chu New
[1/8] RISC-V: Minor cleanup and testcases improvement for arch string parser. RISC-V: Architecture string improvement 0 0 0 2020-11-27 Nelson Chu New
RISC-V: Relax PCREL to GPREL while doing other relaxations is dangerous. RISC-V: Relax PCREL to GPREL while doing other relaxations is dangerous. 0 0 0 2020-11-18 Nelson Chu New
[v2] RISC-V: Update ABI to the elf_flags after parsing elf attributes. [v2] RISC-V: Update ABI to the elf_flags after parsing elf attributes. 0 0 0 2020-11-05 Nelson Chu New
RISC-V: Update ABI to the elf_flags after parsing elf attributes. RISC-V: Update ABI to the elf_flags after parsing elf attributes. 0 0 0 2020-10-20 Nelson Chu New
[v3,2/2] RISC-V: Fix that IRELATIVE relocs may be inserted to the wrong place. RISC-V: Support GNU indirect functions 0 0 0 2020-10-07 Nelson Chu New
[v3,1/2] RISC-V: Support GNU indirect functions. RISC-V: Support GNU indirect functions 0 0 0 2020-10-07 Nelson Chu New
RISC-V: Treat R_RISCV_CALL and R_RISCV_CALL_PLT as the same in check_relocs. RISC-V: Treat R_RISCV_CALL and R_RISCV_CALL_PLT as the same in check_relocs. 0 0 0 2020-08-26 Nelson Chu New
[3/3] RISC-V: Minor cleanup and typos when merging priv spec attributes. Allow to link objects with different versions of ISA, and fix some minor issues 0 0 0 2020-08-20 Nelson Chu New
[2/3] RISC-V: Report warnings rather than errors for the mis-matched ISA versions. Allow to link objects with different versions of ISA, and fix some minor issues 0 0 0 2020-08-20 Nelson Chu New
[1/3] RISC-V: Improve the error message for the mis-matched ISA versions. Allow to link objects with different versions of ISA, and fix some minor issues 0 0 0 2020-08-20 Nelson Chu New
[v2,8/8] RISC-V: Change bfd_link_executable back to !bfd_link_pic in check_relocs. [v2,1/8] RISC-V: Support GNU indirect functions. 0 0 0 2020-08-07 Nelson Chu New
[v2,7/8] RISC-V: Consider the different module testcases for IFUNC. [v2,1/8] RISC-V: Support GNU indirect functions. 0 0 0 2020-08-07 Nelson Chu New
[v2,6/8] RISC-V: Rewrite the IFUNC testcases. [v2,1/8] RISC-V: Support GNU indirect functions. 0 0 0 2020-08-07 Nelson Chu New
[v2,5/8] RISC-V: Remove the IFUNC testcases since their name are hard to understand. [v2,1/8] RISC-V: Support GNU indirect functions. 0 0 0 2020-08-07 Nelson Chu New
[v2,4/8] RISC-V: Use NEED_IFUNC_SECTIONS to check if we need IFUNC sections or not. [v2,1/8] RISC-V: Support GNU indirect functions. 0 0 0 2020-08-07 Nelson Chu New
[v2,3/8] RISC-V: Resolve the TEXTREL warning and redundant R_RISCV_NONE for IFUNC. [v2,1/8] RISC-V: Support GNU indirect functions. 0 0 0 2020-08-07 Nelson Chu New
[v2,2/8] RISC-V: Treat R_RISCV_CALL and R_RISCV_CALL_PLT as the same. [v2,1/8] RISC-V: Support GNU indirect functions. 0 0 0 2020-08-07 Nelson Chu Superseded
[v2,1/8] RISC-V: Support GNU indirect functions. [v2,1/8] RISC-V: Support GNU indirect functions. 0 0 0 2020-08-07 Nelson Chu New
[v2,0/8] RISC-V: Support GNU indirect functions 0 0 0 2020-08-07 Nelson Chu New
RISC-V: Support GNU indirect functions. RISC-V: Support GNU indirect functions. 0 0 0 2020-07-08 Nelson Chu Superseded
RISC-V: Support GNU indirect functions. RISC-V: Support GNU indirect functions. 0 0 0 2020-07-08 Nelson Chu Superseded
[v2,3/3] RISC-V: Support new CSR macro DECLARE_CSR_REUSE to handle the reused CSR. [v2,1/3] RISC-V: Cleanup the include/opcode/riscv-opc.h. 0 0 0 2020-06-25 Nelson Chu New
[v2,2/3] RISC-V: Support debug and float CSR as the unprivileged ones. [v2,1/3] RISC-V: Cleanup the include/opcode/riscv-opc.h. 0 0 0 2020-06-25 Nelson Chu New
[v2,1/3] RISC-V: Cleanup the include/opcode/riscv-opc.h. [v2,1/3] RISC-V: Cleanup the include/opcode/riscv-opc.h. 0 0 0 2020-06-25 Nelson Chu New
[v2,0/3] Support unprivileged CSR and new DECLARE_CSR_REUSE macro 0 0 0 2020-06-25 Nelson Chu New
[v2] RISC-V: Generate ELF priv attributes if priv instruction are explicited used. [v2] RISC-V: Generate ELF priv attributes if priv instruction are explicited used. 0 0 0 2020-06-22 Nelson Chu New
[2/2] RISC-V: Report warning when linking the objects with different priv specs. RISC-V: Update linker behavior when merging the elf priv spec attributes 0 0 0 2020-06-17 Nelson Chu New
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