Show patches with: Submitter = =?UTF-8?B?5aSP56uL5pa5?=       |    Archived = No       |   12 patches
Patch Series S/W/F Date Submitter Delegate State
RISC-V: Add CSRs and opcodes of the T-HEAD XUANTIE CPUs RISC-V: Add CSRs and opcodes of the T-HEAD XUANTIE CPUs 0 0 0 2021-09-07 =?UTF-8?B?5aSP56uL5pa5?= New
[Integration,2/2] RISC-V: Update csr and opcodes for Xuantie CPUs. RISC-V: Add vendor(T-HEAD) opcodes 0 0 0 2021-09-03 =?UTF-8?B?5aSP56uL5pa5?= New
[Integration,1/2] RISC-V: add vendor opcodes RISC-V: Add vendor(T-HEAD) opcodes 0 0 0 2021-09-03 =?UTF-8?B?5aSP56uL5pa5?= New
PR 28215: [CSKY] Don't abort while immediate overflow PR 28215: [CSKY] Don't abort while immediate overflow 0 0 0 2021-08-10 =?UTF-8?B?5aSP56uL5pa5?= New
PR28168: [CSKY] Fix stack overflow in disassembler PR28168: [CSKY] Fix stack overflow in disassembler 0 0 0 2021-08-10 =?UTF-8?B?5aSP56uL5pa5?= New
回复:[PATCH] RISC-V: PR27566, Do not relax when data segment phase is exp_seg_relro_adjust. 回复:[PATCH] RISC-V: PR27566, Do not relax when data segment phase is exp_seg_relro_adjust. 0 0 0 2021-05-17 =?UTF-8?B?5aSP56uL5pa5?= New
RISC-V: compress "addi d,CV,z" to "c.mv d,CV" RISC-V: compress "addi d,CV,z" to "c.mv d,CV" 0 0 0 2021-04-15 =?UTF-8?B?5aSP56uL5pa5?= New
CSKY: Fix special_function in howto table CSKY: Fix special_function in howto table 0 0 0 2021-04-14 =?UTF-8?B?5aSP56uL5pa5?= New
CSKY: Modify the default target vec CSKY: Modify the default target vec 0 0 0 2018-12-28 =?UTF-8?B?5aSP56uL5pa5?= New
CSKY: About PC relative diff relocation CSKY: About PC relative diff relocation 0 0 0 2018-09-10 =?UTF-8?B?5aSP56uL5pa5?= New
[2/2] RISC-V: Update csr and opcodes for Xuantie CPUs. RISC-V: Add vendor opcodes 0 0 0 2021-08-27 =?UTF-8?B?5aSP56uL5pa5?= Superseded
[1/2] RISC-V: add vendor opcodes RISC-V: Add vendor opcodes 0 0 0 2021-08-27 =?UTF-8?B?5aSP56uL5pa5?= Superseded