Show patches with: State = Action Required       |    Archived = No       |   5529 patches
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Patch Series S/W/F Date Submitter Delegate State
[1/6,ARC] Refactored location where GOT information is collected. Fixes for GlibC port support. 0 0 0 2018-09-13 cupertinomiranda@gmail.com New
[2/6,ARC] Improved robustness. Return FALSE in case of NULL pointer. Fixes for GlibC port support. 0 0 0 2018-09-13 cupertinomiranda@gmail.com New
[3/6,ARC] Make sure global symbol is not an indirect or warning. Fixes for GlibC port support. 0 0 0 2018-09-13 cupertinomiranda@gmail.com New
[4/6,ARC] PLT information was still being generated when symbol was forced_local. Fixes for GlibC port support. 0 0 0 2018-09-13 cupertinomiranda@gmail.com New
[5/6,ARC] Fixes TLS failures related to tls-align. Fixes for GlibC port support. 0 0 0 2018-09-13 cupertinomiranda@gmail.com New
[6/6,ARC] Fixed issue with DTSOFF relocs. Fixes for GlibC port support. 0 0 0 2018-09-13 cupertinomiranda@gmail.com New
[ARC] Entries to Changelog for previous commits. [ARC] Entries to Changelog for previous commits. 0 0 0 2018-10-01 cupertinomiranda@gmail.com New
multibyte encodings in strings multibyte encodings in strings 0 0 0 2018-10-30 m4tze@exitno.de New
[ARC] More fixes for TLS. [ARC] More fixes for TLS. 0 0 0 2018-11-09 cupertinomiranda@gmail.com New
Fixed warning from previous patch. Added Changelog. Fixed warning from previous patch. Added Changelog. 0 0 0 2018-11-09 cupertinomiranda@gmail.com New
Require C99 for bfd Require C99 for bfd 0 0 0 2020-01-29 cbiesinger@chromium.org New
RISCV:Create zmmul extension RISCV:Create zmmul extension 0 0 0 2021-10-28 shihua@iscas.ac.cn Superseded
[v2] Create zmmul extension [v2] Create zmmul extension 0 0 0 2021-11-03 shihua@iscas.ac.cn New
[1/3] RISC-V: Add mininal support for z[fdq]inx RISC-V: Zfinx extension support 0 0 0 2021-10-28 陈嘉炜 New
[2/3] RISC-V: Add instructions and operand set for z[fdq]inx RISC-V: Zfinx extension support 0 0 0 2021-10-28 陈嘉炜 New
[3/3] RISC-V: Add testcases and disassemble support for z[fdq]inx RISC-V: Zfinx extension support 0 0 0 2021-10-28 陈嘉炜 New
[1/4] RISC-V: Fix order check when use 'z*' sub-extensions RISC-V: Support Scalar Cryptography extension 0 0 0 2021-11-02 陈嘉炜 New
[2/4] RISC-V: Minimal support of scalar crypto extension RISC-V: Support Scalar Cryptography extension 0 0 0 2021-11-02 陈嘉炜 Superseded
[3/4] RISC-V: Scalar crypto instructions and operand set RISC-V: Support Scalar Cryptography extension 0 0 0 2021-11-02 陈嘉炜 Superseded
[4/4] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases RISC-V: Support Scalar Cryptography extension 0 0 0 2021-11-02 陈嘉炜 Superseded
[v2,1/3] RISC-V: Minimal support of scalar crypto extension RISC-V: Support Scalar Cryptography extension 0 0 0 2021-11-03 陈嘉炜 Superseded
[v2,2/3] RISC-V: Scalar crypto instructions and operand set RISC-V: Support Scalar Cryptography extension 0 0 0 2021-11-03 陈嘉炜 Superseded
[v2,3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases RISC-V: Support Scalar Cryptography extension 0 0 0 2021-11-03 陈嘉炜 New
[v3,1/3] RISC-V: Minimal support of scalar crypto extension RISC-V: Support Scalar Cryptography extension 0 0 0 2021-11-04 陈嘉炜 New
[v3,2/3] RISC-V: Scalar crypto instructions and operand set RISC-V: Support Scalar Cryptography extension 0 0 0 2021-11-04 陈嘉炜 Superseded
[v3,3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases RISC-V: Support Scalar Cryptography extension 0 0 0 2021-11-04 陈嘉炜 Superseded
[v4,1/3] RISC-V: Minimal support of scalar crypto extension RISC-V: Support Scalar Cryptography extension 0 0 0 2021-11-15 陈嘉炜 New
[v4,2/3] RISC-V: Scalar crypto instructions and operand set RISC-V: Support Scalar Cryptography extension 0 0 0 2021-11-15 陈嘉炜 New
[v4,3/3] RISC-V: Scalar crypto instruction and Entropy Source CSR testcases RISC-V: Support Scalar Cryptography extension 0 0 0 2021-11-15 陈嘉炜 New
[v2,1/3] RISC-V: Add mininal support for z[fdq]inx RISC-V: Zfinx extension support 0 0 0 2021-11-17 陈嘉炜 New
[v2,2/3] RISC-V: Add instructions and operand set for z[fdq]inx RISC-V: Zfinx extension support 0 0 0 2021-11-17 陈嘉炜 New
[v2,3/3] RISC-V: Add testcases for z[fdq]inx RISC-V: Zfinx extension support 0 0 0 2021-11-17 陈嘉炜 New
[1/1] Fix ld error due to lto shared not support. Fix ld error due to lto shared not support. 0 0 0 2021-12-21 陈嘉炜 New
[1/1] RISC-V: Update Scalar Crypto testcases. Update-Scalar-Crypto-testcases 0 0 0 2021-12-22 陈嘉炜 New
[v2,1/1] Fix ld error due to -shared not support. Fix ld error due to '-shared' not support 0 0 0 2021-12-23 陈嘉炜 New
[1/1] RISC-V: Add Smepmp CSR 'mseccfg' define and testcases. Add Smepmp CSR define and testcases. 0 0 0 2021-12-27 陈嘉炜 New
[v2,resend,BFD] Add support for reading msdos (MZ) executables. [v2,resend,BFD] Add support for reading msdos (MZ) executables. 0 0 0 2018-02-10 Zebediah Figura New
[v2,MIPS] GAS: Fix Loongson3 LLSC errata [v2,MIPS] GAS: Fix Loongson3 LLSC errata 0 0 0 2018-12-14 YunQiang Su New
[v3,MIPS] GAS: Fix Loongson3 LLSC errata [v3,MIPS] GAS: Fix Loongson3 LLSC errata 0 0 0 2019-01-05 YunQiang Su New
[1/2,MIPS] default output as r6 when default target as r6 [1/2,MIPS] default output as r6 when default target as r6 0 0 0 2020-01-18 YunQiang Su New
[2/2,MIPS] Fix testcase for MIPSr6 [1/2,MIPS] default output as r6 when default target as r6 0 0 0 2020-01-18 YunQiang Su New
[1/3] MIPS: Fix test failure with FPXX GCC [1/3] MIPS: Fix test failure with FPXX GCC 0 0 0 2021-03-08 YunQiang Su Superseded
[2/3] MIPS: default output r6 object if configured to r6 [1/3] MIPS: Fix test failure with FPXX GCC 0 0 0 2021-03-08 YunQiang Su New
[3/3] MIPS: Fix testcase for MIPSr6 [1/3] MIPS: Fix test failure with FPXX GCC 0 0 0 2021-03-08 YunQiang Su Superseded
MIPS: remove SHT_REL support for NewABI elf backends MIPS: remove SHT_REL support for NewABI elf backends 0 0 0 2021-03-12 YunQiang Su New
[v2,1/3] MIPS: Fix test failure with FPXX GCC MIPS: default output isa rev base on configuration 0 0 0 2021-03-28 YunQiang Su Superseded
[v2,2/3] MIPS: default output r6 object if configured to r6 MIPS: default output isa rev base on configuration 0 0 0 2021-03-28 YunQiang Su New
[v2,3/3] MIPS: Fix testcase for MIPSr6 MIPS: default output isa rev base on configuration 0 0 0 2021-03-28 YunQiang Su Superseded
[v3,1/3] MIPS: Fix test failure with FPXX GCC MIPS: default output isa rev base on configuration 0 0 0 2021-03-28 YunQiang Su New
[v3,2/3] MIPS: default output r6 object if configured to r6 MIPS: default output isa rev base on configuration 0 0 0 2021-03-28 YunQiang Su New
[v3,3/3] MIPS: Fix testcase for MIPSr6 MIPS: default output isa rev base on configuration 0 0 0 2021-03-28 YunQiang Su New
mark .gnu.debuglto_.debug_* as SHT_MIPS_DWARF mark .gnu.debuglto_.debug_* as SHT_MIPS_DWARF 0 0 0 2021-06-24 YunQiang Su New
[RX] Add target rx-*-linux [RX] Add target rx-*-linux 0 0 0 2018-07-30 Yoshinori Sato New
[2/5] RX: include - Add RXv3 support. [1/5] RX: opcode - Add RXv3 instructions. 0 0 0 2018-12-25 Yoshinori Sato New
[3/5] RX: gas - Add RXv3 instruction support. [1/5] RX: opcode - Add RXv3 instructions. 0 0 0 2018-12-25 Yoshinori Sato New
[4/5] RX: bfd - Add RXv3 support. [1/5] RX: opcode - Add RXv3 instructions. 0 0 0 2018-12-25 Yoshinori Sato New
[5/5] RX: binutils - Add RXv3 support. [1/5] RX: opcode - Add RXv3 instructions. 0 0 0 2018-12-25 Yoshinori Sato New
[1/5] RX: opcode - Add RXv3 instructions. [1/5] RX: opcode - Add RXv3 instructions. 0 0 0 2019-01-05 Yoshinori Sato New
h8300: Instruction support level fix h8300: Instruction support level fix 0 0 0 2019-07-21 Yoshinori Sato New
h8300: Fix testcase movfpe / movtpe h8300: Fix testcase movfpe / movtpe 0 0 0 2019-07-21 Yoshinori Sato New
[GAS] RX: Remove unnecessary hyphens [GAS] RX: Remove unnecessary hyphens 0 0 0 2020-01-14 Yoshinori Sato New
ld: Add rx-linux emulation. ld: Add rx-linux emulation. 0 0 0 2020-04-29 Yoshinori Sato New
gas: Change ELF flags initial value in rx-linux gas: Change ELF flags initial value in rx-linux 0 0 0 2020-04-29 Yoshinori Sato New
opcodes/nfp: skip those non-code sections opcodes/nfp: skip those non-code sections 0 0 0 2021-08-24 Yinjun Zhang Superseded
[v2,1/2] opcodes/nfp: add validity check of island and me opcodes/nfp: bug fix for nfp disassembler 0 0 0 2021-08-26 Yinjun Zhang New
[v2,2/2] opcodes/nfp: skip those non-code sections opcodes/nfp: bug fix for nfp disassembler 0 0 0 2021-08-26 Yinjun Zhang New
nfp: Fix a potential out-of-bound access nfp: Fix a potential out-of-bound access 0 0 0 2021-09-03 Yinjun Zhang New
[gas,arm] Add -mwarn-restrict-it [gas,arm] Add -mwarn-restrict-it 0 0 0 2019-12-06 Wilco Dijkstra New
[binutils-gdb,ld,AArch64] Fix group_sections algorithm [PR25665] [binutils-gdb,ld,AArch64] Fix group_sections algorithm [PR25665] 0 0 0 2020-04-30 Wilco Dijkstra New
[1/7] opcodes: LoongArch: explicitly define b{lt/gt/le/ge}z as syntactic sugars Assorted LoongArch fixes 0 0 0 2021-10-25 WANG Xuerui New
[2/7] opcodes: LoongArch: move definition of jr to sugar section Assorted LoongArch fixes 0 0 0 2021-10-25 WANG Xuerui New
[3/7] opcodes: LoongArch: sort loongarch_jmp_opcodes entries by opcodes Assorted LoongArch fixes 0 0 0 2021-10-25 WANG Xuerui New
[4/7] opcodes: LoongArch: make all non-native jumps desugar to canonical b{gt/le}[u] forms Assorted LoongArch fixes 0 0 0 2021-10-25 WANG Xuerui New
[5/7] opcodes: LoongArch: add "ret" instruction to reduce typing Assorted LoongArch fixes 0 0 0 2021-10-25 WANG Xuerui New
[6/7] opcodes: LoongArch: make beq/bne's operand order "rd, rj" to be consistent with all others Assorted LoongArch fixes 0 0 0 2021-10-25 WANG Xuerui New
[7/7] LoongArch: make .text start at 0x10000 Assorted LoongArch fixes 0 0 0 2021-10-25 WANG Xuerui New
[1/1] gdbarch: Add pc_signed field and use it when adjusting BP addresses [1/1] gdbarch: Add pc_signed field and use it when adjusting BP addresses 0 0 0 2018-03-15 Vlad Ivanov New
[gas,arm] Set context table for '.arch_extension' [gas,arm] Set context table for '.arch_extension' 0 0 0 2019-11-27 Vladimir Murzin New
[ARC] don't force _init/_fini as DT_INIT/DT_FINI [ARC] don't force _init/_fini as DT_INIT/DT_FINI 0 0 0 2019-02-01 Vineet Gupta New
sim: riscv: fix build breakage with rvv changes sim: riscv: fix build breakage with rvv changes 0 0 0 2021-10-28 Vineet Gupta Superseded
sim: riscv: fix build breakage with rvv changes sim: riscv: fix build breakage with rvv changes 0 0 0 2021-10-29 Vineet Gupta New
[RFC,1/4] RISC-V: Hypervisor ext: Treat as "Standard" extension riscv/binutils support Hypervisor Extension 0 0 0 2021-12-16 Vineet Gupta New
[RFC,2/4] RISC-V: Hypervisor ext: CSR and Instructions riscv/binutils support Hypervisor Extension 0 0 0 2021-12-16 Vineet Gupta New
[RFC,3/4] RISC-V: Hypervisor ext: tests for new isns/csr and cleanup old csrs riscv/binutils support Hypervisor Extension 0 0 0 2021-12-16 Vineet Gupta New
[RFC,4/4] RISC-V: fix a comment for adding CSR entry and annotate switch-break riscv/binutils support Hypervisor Extension 0 0 0 2021-12-16 Vineet Gupta Superseded
[v1,1/4] RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/tests riscv/binutils support Hypervisor Extension 0 0 0 2021-12-21 Vineet Gupta New
[v1,2/4] RISC-V: Hypervisor ext: support Privileged Spec 1.12 riscv/binutils support Hypervisor Extension 0 0 0 2021-12-21 Vineet Gupta New
[v1,3/4] RISC-V: Hypervisor Ext: Add tests riscv/binutils support Hypervisor Extension 0 0 0 2021-12-21 Vineet Gupta New
[v1,4/4] RISC-V: fix a comment for adding CSR entry and annotate switch-break riscv/binutils support Hypervisor Extension 0 0 0 2021-12-21 Vineet Gupta New
CSKY: About PC relative diff relocation CSKY: About PC relative diff relocation 0 0 0 2018-09-10 =?UTF-8?B?5aSP56uL5pa5?= New
CSKY: Modify the default target vec CSKY: Modify the default target vec 0 0 0 2018-12-28 =?UTF-8?B?5aSP56uL5pa5?= New
CSKY: Fix special_function in howto table CSKY: Fix special_function in howto table 0 0 0 2021-04-14 =?UTF-8?B?5aSP56uL5pa5?= New
RISC-V: compress "addi d,CV,z" to "c.mv d,CV" RISC-V: compress "addi d,CV,z" to "c.mv d,CV" 0 0 0 2021-04-15 =?UTF-8?B?5aSP56uL5pa5?= New
回复:[PATCH] RISC-V: PR27566, Do not relax when data segment phase is exp_seg_relro_adjust. 回复:[PATCH] RISC-V: PR27566, Do not relax when data segment phase is exp_seg_relro_adjust. 0 0 0 2021-05-17 =?UTF-8?B?5aSP56uL5pa5?= New
PR28168: [CSKY] Fix stack overflow in disassembler PR28168: [CSKY] Fix stack overflow in disassembler 0 0 0 2021-08-10 =?UTF-8?B?5aSP56uL5pa5?= New
PR 28215: [CSKY] Don't abort while immediate overflow PR 28215: [CSKY] Don't abort while immediate overflow 0 0 0 2021-08-10 =?UTF-8?B?5aSP56uL5pa5?= New
[1/2] RISC-V: add vendor opcodes RISC-V: Add vendor opcodes 0 0 0 2021-08-27 =?UTF-8?B?5aSP56uL5pa5?= Superseded
[2/2] RISC-V: Update csr and opcodes for Xuantie CPUs. RISC-V: Add vendor opcodes 0 0 0 2021-08-27 =?UTF-8?B?5aSP56uL5pa5?= Superseded
[Integration,1/2] RISC-V: add vendor opcodes RISC-V: Add vendor(T-HEAD) opcodes 0 0 0 2021-09-03 =?UTF-8?B?5aSP56uL5pa5?= New
[Integration,2/2] RISC-V: Update csr and opcodes for Xuantie CPUs. RISC-V: Add vendor(T-HEAD) opcodes 0 0 0 2021-09-03 =?UTF-8?B?5aSP56uL5pa5?= New
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