[RFC,4/5] RISC-V: Add 'flh' and 'fsh' macro instructions

Message ID fb0fcd23d76ecfa468a0d3a62e65d798cbe902ae.1641898063.git.research_trasio@irq.a4lg.com
State New
Headers show
Series
  • RISC-V: Add Half-precision floating point extensions
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Commit Message

H.J. Lu via Binutils Jan. 11, 2022, 10:48 a.m.
This commit adds two new macro instructions 'flh' and 'fsh'.

gas/ChangeLog:

	* config/tc-riscv.c (macro): Add macro instruction handling for
	M_FLH and M_FSH.

include/ChangeLog:

	* opcode/riscv.h (M_FLH, M_FSH): New macro instructions.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add new macro instructions.
---
 gas/config/tc-riscv.c  | 10 ++++++++++
 include/opcode/riscv.h |  2 ++
 opcodes/riscv-opc.c    |  2 ++
 3 files changed, 14 insertions(+)

-- 
2.32.0

Patch

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 390aaf1710b..973230d827b 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1822,6 +1822,11 @@  macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
 		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
       break;
 
+    case M_FLH:
+      pcrel_load (rd, rs1, imm_expr, "flh",
+		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
+      break;
+
     case M_FLW:
       pcrel_load (rd, rs1, imm_expr, "flw",
 		  BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
@@ -1852,6 +1857,11 @@  macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
 		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
       break;
 
+    case M_FSH:
+      pcrel_store (rs2, rs1, imm_expr, "fsh",
+		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
+      break;
+
     case M_FSW:
       pcrel_store (rs2, rs1, imm_expr, "fsw",
 		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index a5da8d0c4e0..4d2acf807c2 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -484,9 +484,11 @@  enum
   M_SH,
   M_SW,
   M_SD,
+  M_FLH,
   M_FLW,
   M_FLD,
   M_FLQ,
+  M_FSH,
   M_FSW,
   M_FSD,
   M_FSQ,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 660ba0a8fe8..a538d95e331 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -649,7 +649,9 @@  const struct riscv_opcode riscv_opcodes[] =
 
 /* Half-precision floating-point instruction subset.  */
 {"flh",        0, INSN_CLASS_ZFHMIN,   "D,o(s)",    MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"flh",        0, INSN_CLASS_ZFHMIN,   "D,A,s",     0, (int) M_FLH, match_never, INSN_MACRO },
 {"fsh",        0, INSN_CLASS_ZFHMIN,   "T,q(s)",    MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"fsh",        0, INSN_CLASS_ZFHMIN,   "T,A,s",     0, (int) M_FSH, match_never, INSN_MACRO },
 {"fmv.x.h",    0, INSN_CLASS_ZFHMIN,   "d,S",       MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
 {"fmv.h.x",    0, INSN_CLASS_ZFHMIN,   "D,s",       MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
 {"fsgnj.h",    0, INSN_CLASS_ZFH,   "D,S,T",     MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },