[1/1] RISC-V: Fix mask for some fcvt instructions

Message ID 3ab20eb4c065dc1e5a976dccc593a2c9a6ab853f.1641802855.git.research_trasio@irq.a4lg.com
State New
Headers show
Series
  • RISC-V: Fix mask for some fcvt instructions
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Commit Message

H.J. Lu via Binutils Jan. 10, 2022, 8:22 a.m.
This commit fixes incorrect uses of mask values in 'fcvt' instruction
family.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Fix incorrect uses of mask values
	in 'fcvt' instruction family.
---
 opcodes/riscv-opc.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

-- 
2.32.0

Comments

Andrew Waterman Jan. 10, 2022, 11:56 p.m. | #1
LGTM.  Thanks.

On Mon, Jan 10, 2022 at 12:23 AM Tsukasa OI via Binutils
<binutils@sourceware.org> wrote:
>

> This commit fixes incorrect uses of mask values in 'fcvt' instruction

> family.

>

> opcodes/ChangeLog:

>

>         * riscv-opc.c (riscv_opcodes): Fix incorrect uses of mask values

>         in 'fcvt' instruction family.

> ---

>  opcodes/riscv-opc.c | 8 ++++----

>  1 file changed, 4 insertions(+), 4 deletions(-)

>

> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c

> index 2da0f7cf0a4..00ee21d783f 100644

> --- a/opcodes/riscv-opc.c

> +++ b/opcodes/riscv-opc.c

> @@ -630,7 +630,7 @@ const struct riscv_opcode riscv_opcodes[] =

>  {"fcvt.wu.s",  0, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },

>  {"fcvt.s.w",   0, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },

>  {"fcvt.s.w",   0, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },

> -{"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },

> +{"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_WU|MASK_RM, match_opcode, 0 },

>  {"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },

>  {"fclass.s",   0, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },

>  {"feq.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,S,T",     MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },

> @@ -644,7 +644,7 @@ const struct riscv_opcode riscv_opcodes[] =

>  {"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },

>  {"fcvt.s.l",  64, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },

>  {"fcvt.s.l",  64, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },

> -{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },

> +{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 },

>  {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },

>

>  /* Double-precision floating-point instruction subset.  */

> @@ -705,7 +705,7 @@ const struct riscv_opcode riscv_opcodes[] =

>  {"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },

>  {"fcvt.d.l",  64, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },

>  {"fcvt.d.l",  64, INSN_CLASS_D_OR_ZDINX,   "D,s,m",     MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },

> -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },

> +{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 },

>  {"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX,   "D,s,m",     MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },

>

>  /* Quad-precision floating-point instruction subset.  */

> @@ -765,7 +765,7 @@ const struct riscv_opcode riscv_opcodes[] =

>  {"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },

>  {"fcvt.q.l",  64, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },

>  {"fcvt.q.l",  64, INSN_CLASS_Q_OR_ZQINX,   "D,s,m",     MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },

> -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },

> +{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 },

>  {"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX,   "D,s,m",     MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },

>

>  /* Compressed instructions.  */

> --

> 2.32.0

>

Patch

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2da0f7cf0a4..00ee21d783f 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -630,7 +630,7 @@  const struct riscv_opcode riscv_opcodes[] =
 {"fcvt.wu.s",  0, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
 {"fcvt.s.w",   0, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
 {"fcvt.s.w",   0, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
-{"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
+{"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_WU|MASK_RM, match_opcode, 0 },
 {"fcvt.s.wu",  0, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
 {"fclass.s",   0, INSN_CLASS_F_OR_ZFINX,   "d,S",       MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
 {"feq.s",      0, INSN_CLASS_F_OR_ZFINX,   "d,S,T",     MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
@@ -644,7 +644,7 @@  const struct riscv_opcode riscv_opcodes[] =
 {"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX,   "d,S,m",     MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
 {"fcvt.s.l",  64, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
 {"fcvt.s.l",  64, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
-{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
+{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX,   "D,s",       MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 },
 {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX,   "D,s,m",     MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
 
 /* Double-precision floating-point instruction subset.  */
@@ -705,7 +705,7 @@  const struct riscv_opcode riscv_opcodes[] =
 {"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX,   "d,S,m",     MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
 {"fcvt.d.l",  64, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
 {"fcvt.d.l",  64, INSN_CLASS_D_OR_ZDINX,   "D,s,m",     MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
-{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
+{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX,   "D,s",       MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 },
 {"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX,   "D,s,m",     MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
 
 /* Quad-precision floating-point instruction subset.  */
@@ -765,7 +765,7 @@  const struct riscv_opcode riscv_opcodes[] =
 {"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
 {"fcvt.q.l",  64, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
 {"fcvt.q.l",  64, INSN_CLASS_Q_OR_ZQINX,   "D,s,m",     MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
-{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
+{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX,   "D,s",       MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 },
 {"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX,   "D,s,m",     MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
 
 /* Compressed instructions.  */