cpu: Fix typos and get ride of "Ctrl-L" character

Message ID 20211120092257.15488-1-ehaouas@noos.fr
State New
Headers show
Series
  • cpu: Fix typos and get ride of "Ctrl-L" character
Related show

Commit Message

Elyes HAOUAS Nov. 20, 2021, 9:22 a.m.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>

---

-- 
2.33.1

Comments

H.J. Lu via Binutils Nov. 20, 2021, 5:56 p.m. | #1
but like, why ?  ^L is a common convention in GNU source files to force
breaks between large chunks of related code.  are you going to try and
strip the ^L from all the files in the tree ?
-mike

Patch

diff --git a/cpu/bpf.opc b/cpu/bpf.opc
index e70ee04841d..b60821a0e7d 100644
--- a/cpu/bpf.opc
+++ b/cpu/bpf.opc
@@ -29,7 +29,7 @@ 
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"
    <arch>-ibd.h additions use: "-- ibd.h".  */
-
+
 /* -- opc.h */
 
 #undef CGEN_DIS_HASH_SIZE
@@ -44,9 +44,9 @@ 
 #define CGEN_VALIDATE_INSN_SUPPORTED
 extern int bpf_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
 
-
+
 /* -- opc.c */
-
+
 /* -- asm.c */
 
 /* Parse a signed 64-bit immediate.  */
@@ -111,7 +111,7 @@  bpf_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
   return cgen_bitset_intersect_p (&isas, cd->isas);
 }
 
-
+
 /* -- dis.c */
 
 /* We need to customize the disassembler a bit:
@@ -186,6 +186,6 @@  print_endsize (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
   (*info->fprintf_func) (info->stream, "%lu", value);
 }
 
-
+
 /* -- */
 
diff --git a/cpu/cris.cpu b/cpu/cris.cpu
index 97b44581e78..48a86a3b2e4 100644
--- a/cpu/cris.cpu
+++ b/cpu/cris.cpu
@@ -1890,7 +1890,7 @@ 
   (setf-arit2 size op source1 source2 result carry cbit)
 )
 
-; Let's have convienence macros for arithmetic, including evaluation of the
+; Let's have convenience macros for arithmetic, including evaluation of the
 ; operation, destination modification, flag setting and carry propagation.
 (define-pmacro
   (cris-arit6-int arit size fdest fdest_op srcop1 srcop2 carryout carryin)
@@ -3458,7 +3458,7 @@ 
 
 ;  ABS     Rs,Rd           [ Rd | 01101011 | Rs ]
 (dni-cdt
- abs "Absolut Instruction"
+ abs "Absolute Instruction"
  "abs $Rs,$Rd"
  (+ Rd MODE_REGISTER RFIX_ABS SIZE_FIXED Rs)
  (sequence
diff --git a/cpu/epiphany.cpu b/cpu/epiphany.cpu
index 02bce0779d5..9e6bdf0bce3 100644
--- a/cpu/epiphany.cpu
+++ b/cpu/epiphany.cpu
@@ -373,7 +373,7 @@ 
 (define-normal-insn-enum post-index "+/- index register" () DIR_ f-addsubx (POSTINC POSTDEC))
 
 (define-normal-insn-enum disp-post-modify "postmodify displacement" () PMOD_ f-pm (DISP POST))
-
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 					; Hardware pieces.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -569,9 +569,9 @@ 
 	   (pc             2) ; virtualized PC
 	   (debug          3);
 	   (iab            4)
-	   (lc             5);loop counter            Not impemented
-	   (ls             6);loop start address      Not impemented
-	   (le             7);loop end address        Not impemented
+	   (lc             5);loop counter            Not implemented
+	   (ls             6);loop start address      Not implemented
+	   (le             7);loop end address        Not implemented
 	   (iret           8)
 	   (imask          9)
 	   (ilat           10)
@@ -1059,9 +1059,9 @@ 
   )
 
 
-;;      (lc             5);loop counter            Not impemented
-;;       (ls             6);loop start address      Not impemented
-;;       (le             7);loop end address        Not impemented
+;;       (lc             5);loop counter            Not implemented
+;;       (ls             6);loop start address      Not implemented
+;;       (le             7);loop end address        Not implemented
 
 ;;have callback to adjust pc in case od events ( HW loops ... )
 (define-pmacro (dni_wrapper isnid stdrdesc attr_ strassembl iopcode proceed null_b)
@@ -1292,7 +1292,7 @@ 
      ()
      )
 
-
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 					;  Load/Store Memory Instructions
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -1772,7 +1772,7 @@ 
 (store-insn strh HI OPW_SHORT store-to-ea)
 (store-insn str  SI OPW_WORD store-to-ea)
 (store-insn strd DI OPW_DOUBLE store-double-to-ea)
-
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; MOV<COND> RD,RN
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -2129,7 +2129,7 @@ 
      ()
      )
 
-
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Integer arithmetic instructions 3 address forms
 ;;   both 16 and 32 bit forms
diff --git a/cpu/epiphany.opc b/cpu/epiphany.opc
index 903eccf275a..5c5544ac01e 100644
--- a/cpu/epiphany.opc
+++ b/cpu/epiphany.opc
@@ -29,7 +29,7 @@ 
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"
    <arch>-ibd.h additions use: "-- ibd.h".  */
-
+
 /* -- opc.h */
 
 /* enumerate relaxation types for gas. */
@@ -83,11 +83,11 @@  extern const char * parse_branch_addr (CGEN_CPU_DESC cd,
 /* Allows reason codes to be output when assembler errors occur.  */
 #define CGEN_VERBOSE_ASSEMBLER_ERRORS
 
-
+
 /* -- opc.c */
 
 
-
+
 /* -- asm.c */
 const char *
 parse_shortregs (CGEN_CPU_DESC cd,
@@ -336,7 +336,7 @@  parse_branch_addr (CGEN_CPU_DESC cd,
     }
   return errmsg;
 }
-
+
 /* -- dis.c */
 
 #define CGEN_PRINT_INSN epiphany_print_insn
@@ -412,6 +412,6 @@  print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
   print_address (cd, dis_info, value, attrs, pc, length);
 }
 
-
+
 /* -- */
 
diff --git a/cpu/fr30.cpu b/cpu/fr30.cpu
index 07bf1daf119..1306e1f1e38 100644
--- a/cpu/fr30.cpu
+++ b/cpu/fr30.cpu
@@ -58,7 +58,7 @@ 
   (comment "Generic FR30 cpu")
   (cpu fr30bf)
 )
-
+
 ; Model descriptions.
 ;
 (define-model
@@ -120,7 +120,7 @@ 
 	() ; profile action (default)
 	)
 )
-
+
 ; The instruction fetch/execute cycle.
 ;
 ; This is how to fetch and decode an instruction.
@@ -132,7 +132,7 @@ 
 ; Leave it out for now
 
 ; (define-execute (const SI 0))
-
+
 ; Instruction fields.
 ;
 ; Attributes:
@@ -229,7 +229,7 @@ 
 (dnf f-reglist_low_st "8 bit register mask for stm" () 8 8)
 (dnf f-reglist_hi_ld  "8 bit register mask for ldm" () 8 8)
 (dnf f-reglist_low_ld "8 bit register mask for ldm" () 8 8)
-
+
 ; Enums.
 
 ; insn-op1: bits 0-3
@@ -270,7 +270,7 @@ 
 (define-normal-insn-enum insn-cc "insn cc enums" () CC_ f-cc
   ("ra" "no" "eq" "ne" "c" "nc" "n" "p" "v" "nv" "lt" "ge" "le" "gt" "ls" "hi")
 )
-
+
 ; Hardware pieces.
 ; These entries list the elements of the raw hardware.
 ; They're also used to provide tables and other elements of the assembly
@@ -399,7 +399,7 @@ 
   (get () (c-call UQI "@cpu@_h_ilm_get_handler"))
   (set (newval) (c-call VOID "@cpu@_h_ilm_set_handler" newval))
 )
-
+
 ; Instruction Operands.
 ; These entries provide a layer between the assembler and the raw hardware
 ; description, and are used to refer to hardware elements in the semantic
@@ -526,7 +526,7 @@ 
 (dnop ccr  "condition code bits"   (SEM-ONLY) h-ccr  f-nil)
 (dnop scr  "system condition bits" (SEM-ONLY) h-scr  f-nil)
 (dnop ilm  "interrupt level mask"  (SEM-ONLY) h-ilm  f-nil)
-
+
 ; Instruction definitions.
 ;
 ; Notes:
@@ -1346,7 +1346,7 @@ 
      "int $u8"
      (+ OP1_1 OP2_F u8)
      (sequence ()
-	       ; This is defered to fr30_int because for the breakpoint case
+	       ; This is deferred to fr30_int because for the breakpoint case
 	       ; we want to change as little of the machine state as possible.
 	       ; Push PS onto the system stack
 	       ;(set  (reg h-dr 2) (sub (reg h-dr 2) (const 4)))
@@ -1377,7 +1377,7 @@ 
      "inte"
      (+ OP1_9 OP2_F OP3_3 OP4_0)
      (sequence ()
-	       ; This is defered to fr30_inte because for the breakpoint case
+	       ; This is deferred to fr30_inte because for the breakpoint case
 	       ; we want to change as little of the machine state as possible.
 	       ; Push PS onto the system stack
 	       ;(set  (reg h-dr 2) (sub (reg h-dr 2) (const 4)))
diff --git a/cpu/fr30.opc b/cpu/fr30.opc
index b09148e1c15..47fe9eac6d2 100644
--- a/cpu/fr30.opc
+++ b/cpu/fr30.opc
@@ -34,7 +34,7 @@ 
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"
    <arch>-ibd.h additions use: "-- ibd.h".  */
-
+
 /* -- opc.h */
 
 /* ??? This can be improved upon.  */
@@ -44,7 +44,7 @@ 
 #define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4)
 
 /* -- */
-
+
 /* -- asm.c */
 /* Handle register lists for LDMx and STMx.  */
 
diff --git a/cpu/frv.cpu b/cpu/frv.cpu
index cdb169eddc1..12677db7216 100644
--- a/cpu/frv.cpu
+++ b/cpu/frv.cpu
@@ -53,7 +53,7 @@ 
   (endian big)
   (word-bitsize 32)
 )
-
+
 ; Generic FR-V machine. Supports the entire architecture
 (define-mach
   (name frv)
@@ -77,7 +77,7 @@ 
 	() ; profile action (default)
 	)
 )
-
+
 ; FR550 machine
 (define-mach
   (name fr550)
@@ -937,7 +937,7 @@ 
 	() ; profile action (default)
 	)
 )
-
+
 ; Tomcat machine. Early version of fr500 machine
 (define-mach
   (name tomcat)
@@ -961,7 +961,7 @@ 
 	() ; profile action (default)
 	)
 )
-
+
 ; FR400 machine
 (define-mach
   (name fr400)
@@ -1338,7 +1338,7 @@ 
 	() ; profile action (default)
 	)
 )
-
+
 ; FR450 machine
 (define-mach
   (name fr450)
@@ -1722,7 +1722,7 @@ 
 	() ; profile action (default)
 	)
 )
-
+
 ; Simple machine - single issue integer machine
 (define-mach
   (name simple)
@@ -1743,7 +1743,7 @@ 
 	() ; profile action (default)
 	)
 )
-
+
 ; The instruction fetch/execute cycle.
 ;
 ; This is how to fetch and decode an instruction.
@@ -1755,7 +1755,7 @@ 
 ; Leave it out for now
 
 ; (define-execute (const SI 0))
-
+
 ; An attribute to describe which unit an insn runs in.
 (define-attr
   (for insn)
@@ -1885,7 +1885,7 @@ 
   (name AUDIO)
   (comment "Audio instruction added with FR405")
 )
-; null attribute -- used as a place holder for where an attribue is required.
+; null attribute -- used as a place holder for where an attribute is required.
 (define-attr
   (for insn)
   (type boolean)
@@ -1907,11 +1907,11 @@ 
    (ALU - () "ALU")
    (FPU - () "FPU")
    (BR - () "Branch")
-   (PRIV - () "Priviledged")
+   (PRIV - () "Privileged")
    (MISC - () "Miscellaneous")
   )
 )
-
+
 ; Instruction fields.
 ;
 ; Attributes:
@@ -2098,7 +2098,7 @@ 
     )
   )
 
-
+
 ; Enums.
 
 ; insn-op:
@@ -2158,7 +2158,7 @@ 
   ("nev" "u" "gt" "ug" "lt" "ul" "lg" "ne"
    "eq" "ue" "ge" "uge" "le" "ule" "o" "ra")
 )
-
+
 ; Hardware pieces.
 ; These entries list the elements of the raw hardware.
 ; They're also used to provide tables and other elements of the assembly
@@ -2911,7 +2911,7 @@ 
   (attrs PROFILE VIRTUAL)
   (type register DI (64))
   (indices extern-keyword acc-names)
-  ; The accumlator is made up of two 32 bit registers, accgi/acci.
+  ; The accumulator is made up of two 32 bit registers, accgi/acci.
   ; We want to extract this as a combined 40 signed bits
   (get (index)
        (or DI
@@ -2935,7 +2935,7 @@ 
   (attrs PROFILE VIRTUAL)
   (type register UDI (64))
   (indices extern-keyword acc-names)
-  ; The accumlator is made up of two 32 bit registers, accgi/acci.
+  ; The accumulator is made up of two 32 bit registers, accgi/acci.
   ; We want to extract this as a combined 40 unsigned bits
   (get (index)
        (or DI
@@ -3035,7 +3035,7 @@ 
   (type register UQI (8))
   (indices extern-keyword cccr-names)
 )
-
+
 ; Dummy hardware used to define packing bit on insns
 ;
 (define-hardware
@@ -3066,7 +3066,7 @@ 
   ; '3'.
   (values keyword "" (("" 0) ("" 1) ("" 2) ("" 3)))
 )
-
+
 ; Instruction Operands.
 ; These entries provide a layer between the assembler and the raw hardware
 ; description, and are used to refer to hardware elements in the semantic
@@ -3363,7 +3363,7 @@ 
 
 (define-pmacro (LI-on)       (f-LI-on  1))
 (define-pmacro (LI-off)      (f-LI-off 0))
-
+
 ; Instruction definitions.
 ;
 ; Notes:
@@ -6241,7 +6241,7 @@ 
 (define-pmacro (trap-semantics cond base offset)
   (if cond
       (sequence ()
-		; This is defered to frv_itrap because for the breakpoint
+		; This is deferred to frv_itrap because for the breakpoint
 		; case we want to change as little of the machine state as
 		; possible.
 		;
@@ -6448,7 +6448,7 @@ 
      "break$pack"
      (+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_3 (GRj-null))
      (sequence ()
-	       ; This is defered to frv_break because for the breakpoint
+	       ; This is deferred to frv_break because for the breakpoint
 	       ; case we want to change as little of the machine state as
 	       ; possible.
 	       ;
diff --git a/cpu/frv.opc b/cpu/frv.opc
index 54acb9c902a..4232dbac982 100644
--- a/cpu/frv.opc
+++ b/cpu/frv.opc
@@ -37,7 +37,7 @@ 
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"
    <arch>-ibd.h additions use: "-- ibd.h".  */
-
+
 /* -- opc.h */
 
 #undef  CGEN_DIS_HASH_SIZE
@@ -76,7 +76,7 @@  void frv_vliw_reset      (FRV_VLIW *, unsigned long, unsigned long);
 int  frv_vliw_add_insn   (FRV_VLIW *, const CGEN_INSN *);
 bool spr_valid           (long);
 /* -- */
-
+
 /* -- opc.c */
 #include "opintl.h"
 #include "elf/frv.h"
@@ -489,7 +489,7 @@  match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size)
   return true;
 }
 
-/* Find the next vliw vliw in the table that can accomodate the new insn.
+/* Find the next vliw vliw in the table that can accommodate the new insn.
    If one is found then return it. Otherwise return NULL.  */
 
 static VLIW_COMBO *
@@ -908,7 +908,7 @@  frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
 	  return 0;
 	}
 
-      /* The frv machine supports all packing conbinations.  If we fail,
+      /* The frv machine supports all packing combinations.  If we fail,
 	 to add the insn, then it could not be handled as if it was the fr500.
 	 Just return as if it was handled ok.  */
       if (vliw->mach == bfd_mach_frv)
@@ -927,7 +927,7 @@  spr_valid (long regno)
   return false;
 }
 /* -- */
-
+
 /* -- asm.c */
 inline static const char *
 parse_symbolic_address (CGEN_CPU_DESC cd,
@@ -1859,7 +1859,7 @@  parse_call_label (CGEN_CPU_DESC cd,
 }
 
 /* -- */
-
+
 /* -- dis.c */
 static void
 print_at (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
diff --git a/cpu/ip2k.cpu b/cpu/ip2k.cpu
index f329eab47d1..3d3fffdd8ad 100644
--- a/cpu/ip2k.cpu
+++ b/cpu/ip2k.cpu
@@ -61,7 +61,7 @@ 
   (default-insn-bitsize 16)
   (base-insn-bitsize 16)
 )
-
+
 ; Cpu family definitions.
 
 
@@ -85,7 +85,7 @@ 
   (cpu ip2kbf)
 )
 
-
+
 ; Model descriptions.
 
 (define-model
@@ -104,7 +104,7 @@ 
 
 ; FIXME: It might simplify things to separate the execute process from the
 ; one that updates the PC.
-
+
 ; Instruction fields.
 ;
 ; Attributes:
@@ -141,7 +141,7 @@ 
 ;)
 
 
-
+
 ; Enums.
 
 ; insn-op6: bits 15-10
@@ -160,7 +160,7 @@ 
 ; insn-dir: bit 9
 (define-normal-insn-enum insn-dir "dir enums" () DIR_ f-dir
   ; This bit specifies the polarity of many two-operand instructions:
-  ; TO_W writes result to W regiser  (eg. ADDC W,$fr)
+  ; TO_W writes result to W register  (eg. ADDC W,$fr)
   ; NOTTO_W writes result in general register  (eg. ADDC $fr,W)
   (TO_W NOTTO_W)
 )
@@ -716,7 +716,7 @@ 
      ()
 )
 
-(dni subcw_fr "Subract w/carry W,fr"
+(dni subcw_fr "Subtract w/carry W,fr"
      ()
      "subc W,$fr"
      (+ OP6_SUBC DIR_TO_W fr)
diff --git a/cpu/ip2k.opc b/cpu/ip2k.opc
index 512c3f3aea8..30300b8384a 100644
--- a/cpu/ip2k.opc
+++ b/cpu/ip2k.opc
@@ -28,7 +28,7 @@ 
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"
    <arch>-ibd.h additions use: "-- ibd.h".  */
-
+
 /* -- opc.h */
 
 /* Check applicability of instructions against machines.  */
@@ -48,7 +48,7 @@ 
 
 extern unsigned int ip2k_asm_hash (const char *);
 extern int ip2k_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
-
+
 /* -- opc.c */
 
 #include "safe-ctype.h"
@@ -83,7 +83,7 @@  ip2k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
   return (machs & cd->machs) != 0;
 }
 
-
+
 /* -- asm.c */
 
 static const char *
diff --git a/cpu/iq10.cpu b/cpu/iq10.cpu
index 252cf5341f7..2f51580ac3d 100644
--- a/cpu/iq10.cpu
+++ b/cpu/iq10.cpu
@@ -116,7 +116,7 @@ 
 		      (set rt (add pc 8))
 		      (set pc jmptarg)))
      ())
-
+
 ; Branch instructions.
 
 (dni bbil "branch bit immediate likely" (MACH10 USES-RS)
@@ -307,7 +307,7 @@ 
      (unimp crcp)
      ())
 
-
+
 ; Special Instructions
 
 (dni avail "Mark Header Buffer Available" (MACH10 USES-RD)
@@ -1109,4 +1109,4 @@ 
      "wbiu $rs,$rt,$bytecount"
      (emit wbiu (f-rd 0) rs rt bytecount)
 )
-
+
diff --git a/cpu/iq2000.cpu b/cpu/iq2000.cpu
index cb9cfae1d43..d0b41db7a03 100644
--- a/cpu/iq2000.cpu
+++ b/cpu/iq2000.cpu
@@ -93,7 +93,7 @@ 
 (define-pmacro MACH2000 (MACH iq2000))
 (define-pmacro MACH10 (MACH iq10))
 
-
+
 ; Hardware elements.
 
 (define-hardware
@@ -137,7 +137,7 @@ 
 	     (else (set (raw-reg h-gr idx) newval))))
 )
 
-
+
 ; Instruction fields.
 
 (dnf f-opcode   "opcode field"                  ()  31  6)
@@ -231,7 +231,7 @@ 
 (dnf f-cm-3z   "CM 3Z field"        ()    1  2)
 (dnf f-cm-4z   "CM 4Z field"        ()    2  3)
 
-
+
 ; Enumerations.
 
 (define-normal-insn-enum
@@ -312,7 +312,7 @@ 
    (("CAM36" 16) ("CAM72" 17) ("CAM144" 18) ("CAM288" 19))
 )
 
-
+
 ; Attributes.
 
 (define-attr
@@ -355,7 +355,7 @@ 
 (define-reg-use-attr "rt")
 (define-reg-use-attr "r31")
 
-
+
 ; Operands.
 
 (dnop rs       "register Rs"             () h-gr    f-rs)
@@ -433,7 +433,7 @@ 
   (handlers (parse "jtargq10"))
 )
 
-
+
 ; Instructions.
 
 ; A pmacro for use in semantic bodies of unimplemented insns.
@@ -791,7 +791,7 @@ 
      (set rt (xor rs (zext SI lo16)))
      ())
 
-
+
 ; Branch instructions.
 
 (dni bbi "branch bit immediate" (USES-RS)
@@ -949,9 +949,9 @@ 
 	 (skip 1))
      ())
 
-
 
-
+
+
 ; Jump instructions.
 ; Might as well jump!
 
@@ -970,7 +970,7 @@ 
      (delay 1 (set pc rs))
      ())
 
-
+
 ; Load instructions.
 
 (dni lb "load byte" (LOAD-DELAY USES-RS USES-RT)
@@ -1027,7 +1027,7 @@ 
     (set rt (mem SI (add base (ext SI (trunc HI lo16)))))
     ())
 
-
+
 ; Store instructions.
 
 (dni sb "store byte" (USES-RS USES-RT)
@@ -1048,7 +1048,7 @@ 
      (set (mem SI (add base (ext SI (trunc HI lo16)))) rt)
      ())
 
-
+
 ; Special instructions for simulation/debugging
 (dni break "breakpoint" ()
      "break"
diff --git a/cpu/iq2000.opc b/cpu/iq2000.opc
index f1803737370..e094ae08b9a 100644
--- a/cpu/iq2000.opc
+++ b/cpu/iq2000.opc
@@ -35,7 +35,7 @@ 
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"
    <arch>-ibd.h additions use: "-- ibd.h".  */
-
+
 /* -- opc.h */
 
 /* Allows reason codes to be output when assembler errors occur.  */
diff --git a/cpu/lm32.cpu b/cpu/lm32.cpu
index ecd8160816e..bd1f68469e2 100644
--- a/cpu/lm32.cpu
+++ b/cpu/lm32.cpu
@@ -30,7 +30,7 @@ 
   (isas lm32)
 )
 
-
+
 ; Instruction sets.
 
 (define-isa
@@ -42,7 +42,7 @@ 
   (decode-assist (31 30 29 28 27 26))
 )
 
-
+
 ; Cpu family definitions.
 
 (define-cpu
@@ -67,7 +67,7 @@ 
     1 1 () () () ())
 ) 
 
-
+
 ; Hardware elements.
 
 (dnh h-pc "Program counter" (PC) (pc) () () ())
@@ -111,7 +111,7 @@ 
   () ()
 )              
   
-
+
 ; Instruction fields.
 
 (dnf f-opcode   "opcode field"                () 31  6)
@@ -139,13 +139,13 @@ 
 				    #x8000000)))
 )
 
-
+
 ; Operands.
 
 (dnop r0        "register 0"            () h-gr         f-r0)
 (dnop r1        "register 1"            () h-gr         f-r1)
 (dnop r2        "register 2"            () h-gr         f-r2)
-(dnop shift     "shift amout"           () h-uint       f-shift)
+(dnop shift     "shift amount"          () h-uint       f-shift)
 (dnop imm       "signed immediate"      () h-sint       f-imm)
 (dnop uimm      "unsigned immediate"    () h-uint       f-uimm)
 (dnop branch    "branch offset"         () h-iaddr      f-branch)
@@ -208,7 +208,7 @@ 
   (handlers (parse "gotoff_lo16"))
 )
 
-
+
 ; Enumerations.
 
 (define-normal-insn-enum
@@ -277,7 +277,7 @@ 
   )
 )
  
-
+
 ; Instructions. Note: Reg-reg must come before reg-imm.
 
 (dni add "add" ()
diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu
index ab65fc13626..c938b7f2c4a 100644
--- a/cpu/m32c.cpu
+++ b/cpu/m32c.cpu
@@ -163,7 +163,7 @@ 
 (define-pmacro RL_1ADDR (RL_TYPE 1ADDR))
 (define-pmacro RL_2ADDR (RL_TYPE 2ADDR))
 
-
+
 ;=============================================================
 ; Fields
 ;-------------------------------------------------------------
@@ -1021,7 +1021,7 @@ 
 					    (ifield f-7-1)))
 		)
 )
-
+
 ;=============================================================
 ; Hardware
 ;
@@ -1674,7 +1674,7 @@ 
   (attrs m32c-isa MACH32)
   (type register SI)
 )
-
+
 ;=============================================================
 ; Operands
 ;-------------------------------------------------------------
@@ -2238,7 +2238,7 @@ 
 (dnop SrcIndex "Source Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-src-index f-nil)
 (dnop DstIndex "Destination Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-dst-index f-nil)
 (dnop NoRemainder "Place holder for when the remainder is not kept" (SEM-ONLY MACH32 m32c-isa) h-none f-nil)
-
+
 ;=============================================================
 ; Derived Operands
 
@@ -4176,7 +4176,7 @@ 
 (bit32-absolute 24   Prefixed 12 16)
 
 ;-------------------------------------------------------------
-; Destination operands for short fomat insns
+; Destination operands for short format insns
 ;-------------------------------------------------------------
 
 (define-derived-operand
@@ -5965,7 +5965,7 @@ 
             (set-z x)
             (set-s x))
 )
-
+
 ;=============================================================
 ; Unary insn macros
 ;-------------------------------------------------------------
@@ -7224,7 +7224,7 @@ 
     (insn32-imm1-imm2-dst-Unprefixed-defn HI .w 1 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem)
   )
 )
-
+
 ;=============================================================
 ; Insn definitions
 ;-------------------------------------------------------------
@@ -10298,7 +10298,7 @@ 
 (binary-arith32-imm-dst-defn HI HI .w 1 stz X #x9 #x0 #xF stz-sem)
 
 ;-------------------------------------------------------------
-; stzx - store on zero extention
+; stzx - store on zero extension
 ;-------------------------------------------------------------
 
 (define-pmacro (stzx-sem mode src1 src2 dst)
diff --git a/cpu/m32c.opc b/cpu/m32c.opc
index 2796e1c1cff..04937ea41aa 100644
--- a/cpu/m32c.opc
+++ b/cpu/m32c.opc
@@ -36,7 +36,7 @@ 
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"
    <arch>-ibd.h additions use: "-- ibd.h".  */
-
+
 /* -- opc.h */
 
 /* Needed for RTL's 'ext' and 'trunc' operators.  */
@@ -56,7 +56,7 @@  extern int m32c_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
 #define CGEN_ASM_HASH(mnem) m32c_asm_hash ((mnem))
 
 /* -- */
-
+
 /* -- opc.c */
 static unsigned int
 m32c_asm_hash (const char *mnem)
@@ -79,7 +79,7 @@  m32c_asm_hash (const char *mnem)
     h += *mnem;
   return h % CGEN_ASM_HASH_SIZE;
 }
-
+
 /* -- asm.c */
 #include "safe-ctype.h"
 
diff --git a/cpu/m32r.cpu b/cpu/m32r.cpu
index e85b640ea5e..7540cd8a063 100644
--- a/cpu/m32r.cpu
+++ b/cpu/m32r.cpu
@@ -146,7 +146,7 @@ 
 		   (execute $1))
 	 )
 )
-
+
 ; Cpu family definitions.
 
 ; ??? define-cpu-family [and in general "cpu-family"] might be clearer than
@@ -206,7 +206,7 @@ 
   (comment "M32R2 cpu")
   (cpu m32r2f)
 )
-
+
 ; Model descriptions.
 
 ; The meaning of this value is wip but at the moment it's intended to describe
@@ -399,7 +399,7 @@ 
 	() ; profile action (default)
 	)
 )
-
+
 ; The instruction fetch/execute cycle.
 ; This is split into two parts as sometimes more than one instruction is
 ; decoded at once.
@@ -445,7 +445,7 @@ 
 
 ; FIXME: It might simplify things to separate the execute process from the
 ; one that updates the PC.
-
+
 ; Instruction fields.
 ;
 ; Attributes:
@@ -501,7 +501,7 @@ 
   (encode (value pc) (sub WI value (const WI 1)))
   (decode (value pc) (add WI value (const WI 1)))
 )
-
+
 ; Enums.
 
 ; insn-op1: bits 0-3
@@ -517,7 +517,7 @@ 
   ("0" "1" "2" "3" "4" "5" "6" "7"
    "8" "9" "10" "11" "12" "13" "14" "15")
 )
-
+
 ; Hardware pieces.
 ; These entries list the elements of the raw hardware.
 ; They're also used to provide tables and other elements of the assembly
@@ -631,7 +631,7 @@ 
 
 ; FIXME: Later make add get/set specs and support SMP.
 (dsh h-lock  "lock"  () (register BI))
-
+
 ; Instruction Operands.
 ; These entries provide a layer between the assembler and the raw hardware
 ; description, and are used to refer to hardware elements in the semantic
@@ -746,7 +746,7 @@ 
 
 (dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil)
 (dnop accum "accumulator" (SEM-ONLY) h-accum f-nil)
-
+
 ; Instruction definitions.
 ;
 ; Notes while wip:
diff --git a/cpu/m32r.opc b/cpu/m32r.opc
index 30e0956eac4..6620d76a125 100644
--- a/cpu/m32r.opc
+++ b/cpu/m32r.opc
@@ -38,7 +38,7 @@ 
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"
    <arch>-ibd.h additions use: "-- ibd.h"  */
-
+
 /* -- opc.h */
 
 #undef  CGEN_DIS_HASH_SIZE
@@ -58,7 +58,7 @@  extern unsigned int m32r_cgen_dis_hash (const char *, CGEN_INSN_INT);
 #endif
 
 /* -- */
-
+
 /* -- opc.c */
 unsigned int
 m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value)
@@ -82,7 +82,7 @@  m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value)
 }
 
 /* -- */
-
+
 /* -- asm.c */
 static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
 
@@ -236,7 +236,7 @@  parse_ulo16 (CGEN_CPU_DESC cd,
 }
 
 /* -- */
-
+
 /* -- dis.c */
 
 /* Print signed operands with '#' prefixes.  */
diff --git a/cpu/mep-core.cpu b/cpu/mep-core.cpu
index bdc9c622f14..0abf38a2e65 100644
--- a/cpu/mep-core.cpu
+++ b/cpu/mep-core.cpu
@@ -230,7 +230,7 @@ 
 	() ; profile action (default)
 	)
 )
-
+
 ; Hardware elements.
 
 (dnh h-pc "program counter" (PC PROFILE all-mep-isas) (pc) () () ())
@@ -314,7 +314,7 @@ 
   (type register SI (64))
 )
 
-
+
 ; Instruction fields.  Bit numbering reversed.
 
 ; Conventions:
@@ -615,7 +615,7 @@ 
 		(or (sll (ifield f-ccrn-hi) 4)
 		    (ifield f-ccrn-lo))))
   )
-
+
 ; Operands.
 
 ;; Only LABEL, REGNUM, FMAX_FLOAT and FMAX_INT are now relevant for correct
@@ -669,10 +669,10 @@ 
   (name IS_FLOAT)
   (comment "Register contains a floating point value"))
 
-(define-pmacro (dpop name commment attrib hwr field func)
+(define-pmacro (dpop name comment attrib hwr field func)
   (define-full-operand name comment attrib
     hwr DFLT field ((parse func)) () ()))
-(define-pmacro (dprp name commment attrib hwr field pafunc prfunc)
+(define-pmacro (dprp name comment attrib hwr field pafunc prfunc)
   (define-full-operand name comment attrib
     hwr DFLT field ((parse pafunc) (print prfunc)) () ()))
 
@@ -783,7 +783,7 @@ 
   zero "Zero operand" (all-mep-core-isas) h-sint DFLT f-nil
   ((parse "zero")) () ()
 )
-
+
 ; Attributes.
 
 (define-attr
@@ -962,7 +962,7 @@ 
 	  ) ; config-attr-end
 )
 
-
+
 ; Enumerations.
 
 (define-normal-insn-enum major "major opcodes" (all-mep-core-isas) MAJ_
@@ -1059,7 +1059,7 @@ 
       (set xtarg (and zaddr (inv 7)))))
 
 
-
+
 ; pmacros needed for coprocessor modulo addressing.
 
 ; Taken from supplement ``The operation of the modulo addressing'' in
@@ -1089,7 +1089,7 @@ 
 		(or (and rma (inv modulo-mask)) mb1)
 		(add rma (ext SI immed)))))
 
-
+
 ; Instructions.
 
 ; A pmacro for use in semantic bodies of unimplemented insns.
@@ -1346,7 +1346,7 @@ 
      ((mep (unit u-exec)
 	   (unit u-load-gpr (out loadreg rnl)))))
 
-
+
 ; Extension instructions.
 
 (dnci extb "sign extend byte" ()
@@ -1377,7 +1377,7 @@ 
      ((mep (unit u-use-gpr (in usereg rn))
 	   (unit u-exec))))
 
-
+
 ; Shift amount manipulation instructions.
 
 (dnci ssarb "set sar to bytes" ((STALL SSARB) VOLATILE)
@@ -1389,7 +1389,7 @@ 
      ((mep (unit u-use-gpr (in usereg rm))
 	   (unit u-exec))))
 
-
+
 ; Move instructions.
 
 (dnci mov "move" ()
@@ -1429,7 +1429,7 @@ 
      (set rn (sll uimm16 16))
      ())
 
-
+
 ; Arithmetic instructions.
 
 (dnci add3 "add three registers" ()
@@ -1566,7 +1566,7 @@ 
      ((mep (unit u-use-gpr (in usereg rm))
 	   (unit u-exec))))
 
-
+
 ; Logical instructions.
 
 (dnci or "bitwise or" ()
@@ -1622,7 +1622,7 @@ 
      ((mep (unit u-use-gpr (in usereg rm))
 	   (unit u-exec))))
 
-
+
 ; Shift instructions.
 
 (dnci sra "shift right arithmetic" ((STALL INT2))
@@ -1688,7 +1688,7 @@ 
            (unit u-use-gpr (in usereg rm))
 	   (unit u-exec))))
 
-
+
 ; Branch/jump instructions.
 
 (dnci bra "branch" (RELAXABLE)
@@ -1855,7 +1855,7 @@ 
      ((mep (unit u-exec)
 	   (unit u-branch))))
 
-
+
 ; Repeat instructions.
 
 (dnci repeat "repeat specified repeat block" ()
@@ -1880,7 +1880,7 @@ 
 	       (set (reg h-csr 6) 1))
      ())
 
-
+
 ; Control instructions.
 
 ;; special store variants
@@ -2062,7 +2062,7 @@ 
 	    (unit u-exec)
 	    (unit u-ldcb-gpr (out loadreg rn)))))
 
-
+
 ; Bit manipulation instructions.
 ; The following instructions become the reserved instruction when the
 ; bit manipulation option is off.
@@ -2114,7 +2114,7 @@ 
      ((mep (unit u-use-gpr (in usereg rma))
 	   (unit u-exec))))
 
-
+
 ; Data cache instruction.
 
 (dnci cache "cache operations" (VOLATILE)
@@ -2124,7 +2124,7 @@ 
      ((mep (unit u-use-gpr (in usereg rma))
 	   (unit u-exec))))
 
-
+
 ; Multiply instructions.
 ; These instructions become the RI when the 32-bit multiply
 ; instruction option is off.
@@ -2246,7 +2246,7 @@ 
 	   (unit u-multiply)
 	   (unit u-mul-gpr (out resultreg rn)))))
 
-
+
 ; Divide instructions.
 ; These instructions become the RI when the 32-bit divide instruction
 ; option is off.
@@ -2289,7 +2289,7 @@ 
 	   (unit u-divide)
            (unit u-branch))))
 
-
+
 ; Debug functions.
 ; These instructions become the RI when the debug function option is
 ; off.
@@ -2314,7 +2314,7 @@ 
 	       (set dbg (or dbg 1)))
      ())
 
-
+
 ; Leading zero instruction.
 
 (dnci ldz "leading zeroes" (OPTIONAL_LDZ_INSN (STALL INT2))
@@ -2326,7 +2326,7 @@ 
      ((mep (unit u-use-gpr (in usereg rm))
 	   (unit u-exec))))
 
-
+
 ; Absolute difference instruction.
 
 (dnci abs "absolute difference" (OPTIONAL_ABS_INSN (STALL INT2))
@@ -2339,7 +2339,7 @@ 
 	   (unit u-use-gpr (in usereg rn))
 	   (unit u-exec))))
 
-
+
 ; Average instruction.
 
 (dnci ave "average" (OPTIONAL_AVE_INSN (STALL INT2))
@@ -2352,7 +2352,7 @@ 
 	   (unit u-use-gpr (in usereg rn))
 	   (unit u-exec))))
 
-
+
 ; MIN/MAX instructions.
 
 (dnci min "minimum" (OPTIONAL_MINMAX_INSN (STALL INT2))
@@ -2399,7 +2399,7 @@ 
 	   (unit u-use-gpr (in usereg rn))
 	   (unit u-exec))))
 
-
+
 ; Clipping instruction.
 
 (dnci clip "clip" (OPTIONAL_CLIP_INSN (STALL INT2))
@@ -2429,7 +2429,7 @@ 
      ((mep (unit u-use-gpr (in usereg rn))
 	   (unit u-exec))))
 
-
+
 ; Saturation instructions.
 
 (dnci sadd "saturating addition" (OPTIONAL_SAT_INSN (STALL INT2))
@@ -2488,11 +2488,11 @@ 
 	   (unit u-use-gpr (in usereg rn))
 	   (unit u-exec))))
 
-
+
 ; UCI and DSP options are defined in an external file.
 ; See `mep-sample-ucidsp.cpu' for a sample.
 
-
+
 ; Coprocessor instructions.
 
 (dnci swcp "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
@@ -2703,7 +2703,7 @@ 
      ((mep (unit u-use-gpr (in usereg rma))
 	   (unit u-exec))))
 
-
+
 (dnci sbcpm0 "sbcpm0" (OPTIONAL_CP_INSN)
      "sbcpm0 $crn,($rma+),$cdisp10"
      (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x2) cdisp10)
@@ -2979,7 +2979,7 @@ 
      ((mep (unit u-exec)
 	   (unit u-branch))))
 
-
+
 ; An instruction for test instrumentation.
 ; Using a reserved opcode.
 
@@ -3023,7 +3023,7 @@ 
 ; begin core-specific reserved insns
 ; end core-specific reserved insns
 
-
+
 ; Macro instructions.
 
 (dnmi nop "nop"
diff --git a/cpu/mep-rhcop.cpu b/cpu/mep-rhcop.cpu
index 60edb854a8e..85718ee4ad4 100644
--- a/cpu/mep-rhcop.cpu
+++ b/cpu/mep-rhcop.cpu
@@ -86,7 +86,7 @@ 
 (dnf f-code16b "Unsigned immediate"      ((ISA ext_cop1_48,ext_cop1_64))  32 16)
 
 ; ifields for 64-bit insns
-(dnf f-uu8 "Unsused 8 bits"               ((ISA ext_cop1_64))   4  8)
+(dnf f-uu8 "Unused 8 bits"                ((ISA ext_cop1_64))   4  8)
 (dnf f-uu8a "Unused 13 bits"              ((ISA ext_cop1_64))  16  8)
 (dnf f-seg64 "Enumerate 64-bit insns"     ((ISA ext_cop1_64))  24  8)
 (dnf f-code16c "Unsigned immediate"       ((ISA ext_cop1_64))  48 16)
@@ -97,7 +97,7 @@ 
 (dnf f-cpccrm-64 "Core GPR"               ((ISA ext_cop1_64))  36  4)
 (dnf f-code24 "24 Bit Unisgned Immediate" ((ISA ext_cop1_64))  40 24)
 
-
+
 ; Operands for 16-bit insns
 (dnop cpcrn   "cpcrn"  ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrn)
 (dnop cpcrm   "cpcrm"  ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrm)
@@ -120,7 +120,7 @@ 
 (dnop cpcode24 "cpcode24" ((ISA ext_cop1_64)) h-uint f-code24)
 
 
-
+
 ; 16- and 32-bit nops can be defined as normal instructions without
 ; any problems.  nops take no operands, so nops longer than 32 
 ; bits cannot be defined as normal insns since that would result in
@@ -167,7 +167,7 @@ 
       (emit cpf3nop (code16b 0) (code16c 0))
 )
 
-
+
 (define-pmacro (dncp116i xname xcomment xattrs xsyntax xformat xsemantics xtiming)  (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_16))
 (define-pmacro (dncp132i xname xcomment xattrs xsyntax xformat xsemantics xtiming)  (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_32))
 (define-pmacro (dncp148i xname xcomment xattrs xsyntax xformat xsemantics xtiming)  (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_48))
diff --git a/cpu/mep.opc b/cpu/mep.opc
index 6ad0c5879e8..96c75352e53 100644
--- a/cpu/mep.opc
+++ b/cpu/mep.opc
@@ -1162,7 +1162,7 @@  mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
       cop1buflength = 2;
     }
 
-  /* Now we have the distrubution set.  Print them out.  */
+  /* Now we have the distribution set.  Print them out.  */
   status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,
 				 cop1buflength, cop2buflength);
 
@@ -1251,7 +1251,7 @@  mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
       cop1buflength = 6;
     }
 
-  /* Now we have the distrubution set.  Print them out. */
+  /* Now we have the distrubition set.  Print them out. */
   status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,
 				 cop1buflength, cop2buflength);
 
diff --git a/cpu/mt.cpu b/cpu/mt.cpu
index bb987f31d7b..8f971994794 100644
--- a/cpu/mt.cpu
+++ b/cpu/mt.cpu
@@ -47,7 +47,7 @@ 
   (base-insn-bitsize 32)
   (parallel-insns 2)
 )
-
+
 ; Cpu family definitions.
 
 
@@ -96,7 +96,7 @@ 
   (isas mt)
 )
 
-
+
 ; Model descriptions.
 ; Can probably take the u-exec out.  We'll see.
 (define-model
@@ -140,7 +140,7 @@ 
 
 ; FIXME: It might simplify things to separate the execute process from the
 ; one that updates the PC.
-
+
 
 ;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Instruction Fields ;;
@@ -156,14 +156,14 @@ 
 ; f-opc: 6 bit opcode for non-morphosys instructions.
 ; f-msopc: 6 bit opcode for morphosys instructions.
 ; f-imm: flag to indicate use of an immediate operand.  1 if yes, 0 if no.
-; f-sr1: source resgister 1. (also used for MSYS insns)
+; f-sr1: source register 1. (also used for MSYS insns)
 ; f-sr2: source register 2. (also used for MSYS insns)
 ; f-dr: destination register when located in bits 19:16.
 ; f-drrr: destination register when located in bits 15:12. (also for MSYS insns)
 ; f-imm16: 16 bit immediate value when not an offset.
 ; f-imm16a: 16 bit immediate value when it's a pc-rel offset.
 ; f-uu4a: unused 4 bit field.
-; f-uu4b: second unsed 4 bit field.
+; f-uu4b: second unused 4 bit field.
 ; f-uu1: unused 1 bit field
 ; f-uu12: unused 12 bit field.
 ; f-uu16: unused 16 bit field.
@@ -171,7 +171,7 @@ 
 
 (dnf f-msys      "morphosys insn flag"  	() 31 1)
 (dnf f-opc       "opcode field"			() 30 6)
-(dnf f-imm       "immedate flag"		() 24 1)
+(dnf f-imm       "immediate flag"		() 24 1)
 (dnf f-uu24      "unused 24 bits"               () 23 24)
 (dnf f-sr1       "sr1 register field"	(ABS-ADDR) 23 4)
 (dnf f-sr2       "sr2 register field"	(ABS-ADDR) 19 4)
@@ -251,14 +251,14 @@ 
 (dnf f-cb2sel    "cb2 select"                   () 22 3)
 (dnf f-cb1incr   "cb1 increment"                (SIGNED) 19 6)
 (dnf f-cb2incr   "cb2 increment"                (SIGNED) 13 6)
-(dnf f-rc3       "row/colum context"            ()  7 1)
+(dnf f-rc3       "row/column context"            ()  7 1)
 
 ; The following is just for a test
 (dnf f-msysfrsr2 "sr2 for msys"			() 19 4)
 (dnf f-brc2      "b_r_c2"                       () 14 3)
 (dnf f-ball2     "b_all2"                       () 15 1)
 
-
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Enumerations Of Instruction Fields ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -553,7 +553,7 @@ 
 (define-operand (name cb2incr) (comment "cb2incr") (attrs (MACH ms2))
   (type h-sint) (index f-cb2incr) (handlers (print "dollarhex")))
 
-; Probaby won't need most of these.
+; Probably won't need most of these.
 (define-pmacro r0    (reg h-spr #x0))
 (define-pmacro r1    (reg h-spr #x01))
 (define-pmacro r2    (reg h-spr #x02))
@@ -1236,7 +1236,7 @@ 
      ()
 )
 
-;; Issue 66262: The documenatation gives the wrong order for 
+;; Issue 66262: The documentation gives the wrong order for 
 ;;               the arguments to the WFBINC instruction.
 (dni wfbinc "WFBINC type, ccb/rcb, incr, all, c/r, length, rca_row, word, dup, ctxt_disp"
      ((MACH ms1-003,ms2))
diff --git a/cpu/mt.opc b/cpu/mt.opc
index d988cc25e90..1dcd9b45b33 100644
--- a/cpu/mt.opc
+++ b/cpu/mt.opc
@@ -29,7 +29,7 @@ 
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"
    <arch>-ibd.h additions use: "-- ibd.h"  */
-
+
 /* -- opc.h */
 
 /* Check applicability of instructions against machines.  */
@@ -50,7 +50,7 @@  extern unsigned int mt_asm_hash (const char *);
 
 extern int mt_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
 
-
+
 /* -- opc.c */
 #include "safe-ctype.h"
 
@@ -84,7 +84,7 @@  mt_asm_hash (const char* insn)
   return hash % CGEN_ASM_HASH_SIZE;
 }
 
-
+
 /* -- asm.c */
 /* Range checking for signed numbers.  Returns 0 if acceptable
    and 1 if the value is out of bounds for a signed quantity.  */
diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu
index 9784f7a0fa8..39d29de10cb 100644
--- a/cpu/or1k.cpu
+++ b/cpu/or1k.cpu
@@ -21,7 +21,7 @@ 
 (include "simplify.inc")
 
 ; The OpenRISC family is a set of RISC microprocessor architectures with an
-; emphasis on scalability and is targetted at embedded use.
+; emphasis on scalability and is targeted at embedded use.
 ; The CPU RTL development is a collaborative open source effort.
 ; http://opencores.org/or1k
 ; http://openrisc.net
diff --git a/cpu/or1korbis.cpu b/cpu/or1korbis.cpu
index a8002a37185..cb1d9a4e4e6 100644
--- a/cpu/or1korbis.cpu
+++ b/cpu/or1korbis.cpu
@@ -295,7 +295,7 @@ 
     )
 )
 
-
+
 ; Instruction operands.
 
 (dnop sys-sr            "supervision register"             ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr            f-nil)
@@ -379,7 +379,7 @@ 
 
 ; Instructions.
 
-; Branch releated instructions 
+; Branch related instructions 
 
 (define-pmacro (cti-link-return)
   (set IAI (reg h-gpr 9) (add pc (if sys-cpucfgr-nd 4 8)))
@@ -557,7 +557,7 @@ 
      ()
 )
 
-
+
 ; Misc instructions
 
 ; l.nop with immediate must be first so it handles all l.nops in sim
@@ -602,8 +602,8 @@ 
      ()
 )
 
-
-; System releated instructions
+
+; System related instructions
 
 (dni l-mfspr "mfspr"
      ((MACH ORBIS-MACHS))
@@ -621,7 +621,7 @@ 
      ()
 )
 
-
+
 ; Load instructions
 (define-pmacro (load-store-addr base offset size)
   (c-call AI "@cpu@_make_load_store_addr" base (ext SI offset) size))
@@ -687,7 +687,7 @@ 
      ()
 )
 
-
+
 ; Store instructions
 
 (define-pmacro (store-insn mnemonic opc-op mode size)
@@ -728,7 +728,7 @@ 
      ()
 )
 
-
+
 ; Shift and rotate instructions
 
 (define-pmacro (shift-insn mnemonic)
@@ -758,7 +758,7 @@ 
 (shift-insn sra)
 (shift-insn ror)
 
-
+
 ; Arithmetic insns
 
 ; ALU op macro
diff --git a/cpu/sh.cpu b/cpu/sh.cpu
index d9ece1a03ef..6b1118d53b3 100644
--- a/cpu/sh.cpu
+++ b/cpu/sh.cpu
@@ -33,7 +33,7 @@ 
   (isas compact media)
 )
 
-
+
 ; Instruction sets.
 
 (define-isa
@@ -48,7 +48,7 @@ 
   (base-insn-bitsize 16)
 )
 
-
+
 ; CPU family.
 
 (define-cpu
@@ -57,7 +57,7 @@ 
   (endian either)
   (word-bitsize 32)
 )
-
+
 
 (define-mach
   (name sh2)
@@ -102,7 +102,7 @@ 
 	1 1 ; issue done
 	() () () ())
 )
-
+
 ; Hardware elements.
 
 (define-hardware
@@ -324,7 +324,7 @@ 
   (set (newval) (error "cannot set ism directly"))
 )
 
-
+
 ; Operands.
 
 (dnop endian "Endian mode" ((ISA compact,media)) h-endian f-nil)
@@ -358,7 +358,7 @@ 
 			  (or (sll (zext DI b1) 8)
 			      (zext DI b0)))))))))
 
-
+
 ; Include the two instruction set descriptions from their respective
 ; source files.
 
diff --git a/cpu/sh.opc b/cpu/sh.opc
index 364fcccf647..aa05f167682 100644
--- a/cpu/sh.opc
+++ b/cpu/sh.opc
@@ -37,7 +37,7 @@ 
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"
    <arch>-ibd.h additions use: "-- ibd.h"  */
-
+
 /* -- opc.h */
 
 /* Allows reason codes to be output when assembler errors occur.  */
diff --git a/cpu/sh64-compact.cpu b/cpu/sh64-compact.cpu
index 5b1b8633028..3281b574d75 100644
--- a/cpu/sh64-compact.cpu
+++ b/cpu/sh64-compact.cpu
@@ -21,7 +21,7 @@ 
 ; along with this program; if not, write to the Free Software
 ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
 ; MA 02110-1301, USA.
-
+
 ; dshcf -- define-normal-sh-compact-field
 
 (define-pmacro (dshcf xname xcomment ignored xstart xlength)
@@ -32,7 +32,7 @@ 
 (define-pmacro (dshcop xname xcomment ignored xhardware xfield)
   (dnop xname xcomment ((ISA compact)) xhardware xfield))
 
-
+
 ; SHcompact-specific attributes.
 
 (define-attr
@@ -187,7 +187,7 @@ 
   (set (newval) (set (raw-reg h-gr 19) (or (and (raw-reg h-gr 19) (inv DI 1)) (zext DI newval))))
 )
 
-
+
 (dshcf f-op4     "Opcode (4 bits)"         ()  15   4)
 (dshcf f-op8     "Opcode (8 bits)"         ()  15   8)
 (dshcf f-op16    "Opcode (16 bits)"        ()  15  16)
@@ -252,7 +252,7 @@ 
     ((value pc) (srl SI value 1))
     ((value pc) (add SI (sll SI value 1) 1)))
 
-
+
 ; Operands.
 
 (dshcop rm     "Left general purpose register"          ()   h-grc   f-rm)
@@ -307,7 +307,7 @@ 
 
 (define-operand (name fsdn) (comment "bar")
   (attrs (ISA compact)) (type h-frc) (index f-rn))
-
+
 
 ; Cover macro to dni to indicate these are all SHcompact instructions.
 ; dshmi: define-normal-sh-compact-insn
@@ -323,7 +323,7 @@ 
 
 (define-pmacro (dr operand) (reg h-dr (index-of operand)))
 (define-pmacro (xd x) (reg h-xd (and (index-of x) (inv QI 1))))
-
+
 (dshci add "Add"
        ()
        "add $rm, $rn"
@@ -1712,7 +1712,7 @@ 
        (+ (f-op8 #xc8) uimm8)
        (set tbit (if BI (eq (and r0 (zext SI uimm8)) 0) 1 0)))
 
-(dshci tstb "Test and set t-bit immedate with memory byte"
+(dshci tstb "Test and set t-bit immediate with memory byte"
        ()
        "tst.b #$imm8, @(r0, gbr)"
        (+ (f-op8 #xcc) imm8)
diff --git a/cpu/sh64-media.cpu b/cpu/sh64-media.cpu
index 80dd74a89fb..0e4af354491 100644
--- a/cpu/sh64-media.cpu
+++ b/cpu/sh64-media.cpu
@@ -22,7 +22,7 @@ 
 ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
 ; MA 02110-1301, USA.
 
-
+
 ; dshmf -- define-normal-sh-media-field
 
 (define-pmacro (dshmf xname xcomment ignored xstart xlength)
@@ -66,7 +66,7 @@ 
 	  i
 	  (sub mode (sll mode 1 n) 1))))
 
-
+
 ; Ifields.
 
 (dshmf f-op          "Opcode"                       ()  31  6)
@@ -131,7 +131,7 @@ 
     ((value pc) (sra DI value 2))
     ((value pc) (add DI (sll DI value 2) pc)))
 
-
+
 ; Operands.
 
 (dshmop rm        "Left general purpose reg"            ()  h-gr    f-left)
@@ -181,7 +181,7 @@ 
 (define-operand (name likely) (comment "Likely branch?") (attrs (ISA media))
   (type h-uint) (index f-likely) (handlers (parse "likely") (print "likely")))
 
-
+
 ; Instructions.
 
 (dshmi add "Add"
@@ -435,7 +435,7 @@ 
        (+ (f-op 12) frg (f-ext 10) frh rd (f-rsvd 0))
        (set rd (zext DI (c-call BI "sh64_fcmpuns" frg frh))))
 
-(dshmi fcnvds "Floating point coversion (double to single)"
+(dshmi fcnvds "Floating point conversion (double to single)"
        ()
        "fcnv.ds $drgh, $frf"
        (+ (f-op 14) drgh (f-ext 7) frf (f-rsvd 0))
@@ -843,7 +843,7 @@ 
        (+ (f-op 16) rm (f-ext 1) rn rd (f-rsvd 0))
        (set rd (ext DI (mem HI (add rm rn)))))
 
-
+
 ; Macros to facilitate multimedia instructions.
 
 (define-pmacro (slice-byte expr)
diff --git a/cpu/simplify.inc b/cpu/simplify.inc
index 808018dc83d..fe8856dd04a 100644
--- a/cpu/simplify.inc
+++ b/cpu/simplify.inc
@@ -20,7 +20,7 @@ 
 ; along with this program; if not, write to the Free Software
 ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
 ; MA 02110-1301, USA.
-
+
 ; Enums.
 
 ; Define a normal enum without using name/value pairs.
@@ -38,7 +38,7 @@ 
   "Define a normal instruction opcode enum."
   (define-full-insn-enum name comment attrs prefix fld vals)
 )
-
+
 ; Instruction fields.
 
 ; Normally, fields are unsigned and have no encode/decode needs.
@@ -81,7 +81,7 @@ 
   "Define a simple multi-part instruction field."
   (define-full-multi-ifield name comment attrs UINT subflds #f #f)
 )
-
+
 ; Hardware.
 
 ; Simpler version for most hardware elements.
@@ -119,7 +119,7 @@ 
   "Shorthand form of define-simple-hardware."
   define-simple-hardware
 )
-
+
 ; Operands.
 
 ; Simpler version for most operands.
@@ -161,7 +161,7 @@ 
     (setter x-setter)
     )
 )
-
+
 ; Instructions.
 
 ; Define an instruction object, normal version.
@@ -181,7 +181,7 @@ 
   "Shorthand form of define-normal-insn."
   define-normal-insn
 )
-
+
 ; Macro instructions.
 
 ; Define a macro-insn object, normal version.
@@ -198,7 +198,7 @@ 
   "Shorthand form of define-normal-macro-insn."
   define-normal-macro-insn
 )
-
+
 ; Modes.
 ; ??? Not currently available for use.
 ;
diff --git a/cpu/xc16x.cpu b/cpu/xc16x.cpu
index 4903b814c91..b1a1b9ed71a 100644
--- a/cpu/xc16x.cpu
+++ b/cpu/xc16x.cpu
@@ -647,7 +647,7 @@ 
   (attrs META)
   (values
    (MOVE - () "Data Movement")
-   (ALU  - () "Arithmatic & logical")
+   (ALU  - () "Arithmetic & logical")
    (CMP  - () "Compare")
    (JMP  - () "Jump & Call")
    (MISC - () "Miscellaneous")
@@ -658,7 +658,7 @@ 
 ; Include the instruction set descriptions from their respective
 ; source files.
 
-;Arithmatic insns
+;Arithmetic insns
 ;******************************************************************
 
 ;add/sub register and immediate
diff --git a/cpu/xc16x.opc b/cpu/xc16x.opc
index 47b7c690e43..d07c9ca8adb 100644
--- a/cpu/xc16x.opc
+++ b/cpu/xc16x.opc
@@ -37,18 +37,18 @@ 
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"
    <arch>-ibd.h additions use: "-- ibd.h"  */
-
+
 /* -- opc.h */
 
 #define CGEN_DIS_HASH_SIZE 8
 #define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 3) % CGEN_DIS_HASH_SIZE)
 
 /* -- */
-
+
 /* -- opc.c */
                                                                                 
 /* -- */
-
+
 /* -- asm.c */
 /* Handle '#' prefixes (i.e. skip over them).  */
 
@@ -146,7 +146,7 @@  parse_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
   return _("Missing 'seg:' prefix");
 }
 /* -- */
-
+
 /* -- dis.c */
 
 /* Print an operand with a "." prefix.
diff --git a/cpu/xstormy16.cpu b/cpu/xstormy16.cpu
index aa5a464fa61..cfbe38ec3ea 100644
--- a/cpu/xstormy16.cpu
+++ b/cpu/xstormy16.cpu
@@ -80,11 +80,11 @@ 
    (ALU - () "ALU")
    (FPU - () "FPU")
    (BR - () "Branch")
-   (PRIV - () "Priviledged")
+   (PRIV - () "Privileged")
    (MISC - () "Miscellaneous")
   )
 )
-
+
 ; Hardware elements.
 
 (define-hardware
@@ -192,7 +192,7 @@ 
   (values keyword "" ((".b" 0) (".w" 1) ("" 1)))
 )
 	
-
+
 ; Instruction fields, and the corresponding operands.
 ; Register fields
 
@@ -420,7 +420,7 @@ 
 (dnop R1 "R1" (SEM-ONLY) h-gr 1)
 (dnop R2 "R2" (SEM-ONLY) h-gr 2)
 (dnop R8 "R8" (SEM-ONLY) h-gr 8)
-
+
 ; Useful macros.
 
 ; THe Z8, Z16, PT, and S flags of the PSW.
@@ -532,7 +532,7 @@ 
     (set tmpfoo (ror tmpfoo (and rot #x0F)))
     (set-psw-carry (reg HI h-gr index) index (trunc HI tmpfoo) (and (srl tmpfoo 16) 1) 1)))
 
-
+
 ; Move Operations
 
 (define-pmacro (alignfix-mem where)
@@ -941,7 +941,7 @@ 
 		   (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add (join SI HI Rb Rs) imm12))) ws2))
 	       (set Rs (add Rs (add ws2 1)))
 	       ; Note - despite the XStormy16 ISA documentation the
-	       ; addition *is* propogated into the base register.
+	       ; addition *is* propagated into the base register.
 	       (if (eq Rs 0) (set Rb (add Rb 1)))
 	       )
      ()
@@ -954,7 +954,7 @@ 
      (+ OP1_6 OP2A_C ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12)
      (sequence ()
 	       ; Note - despite the XStormy16 ISA documentation the
-	       ; subtraction *is* propogated into the base register.
+	       ; subtraction *is* propagated into the base register.
 	       (if (eq Rs 0) (set Rb (sub Rb 1)))
 	       (set Rs (sub Rs (add ws2 1)))
 	       (if ws2
@@ -990,7 +990,7 @@ 
 	       (set-psw-nowrite (index-of Rdm) Rdm ws2)
 	       (set Rs (add Rs (add ws2 1)))
 	       ; Note - despite the XStormy16 ISA documentation the
-	       ; addition *is* propogated into the base register.
+	       ; addition *is* propagated into the base register.
 	       (if (eq Rs 0) (set Rb (add Rb 1)))
 	       )
      ()
@@ -1003,7 +1003,7 @@ 
      (+ OP1_6 OP2A_E ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12)
      (sequence ()
 	       ; Note - despite the XStormy16 ISA documentation the
-	       ; subtraction *is* propogated into the base register.
+	       ; subtraction *is* propagated into the base register.
 	       (if (eq Rs 0) (set Rb (sub Rb 1)))
 	       (set Rs (sub Rs (add ws2 1)))
 	       (set-psw-nowrite (index-of Rdm) Rdm ws2)
@@ -1030,7 +1030,7 @@ 
      (set-psw Rd (index-of Rd) (or (and Rd (inv imm16)) (and (reg HI h-gr Rpsw) imm16)) 1)
      ()
 )
-
+
 ; Push, Pop
 (dni pushgr
      "Push register"
@@ -1086,7 +1086,7 @@ 
 	       (set-psw Rd (index-of Rd) foo 1))
      ()
 )
-
+
 ; Logical Operations
 (dni andgrgr
      "AND general register with general register"
@@ -1177,7 +1177,7 @@ 
      (set-psw Rd (index-of Rd) (inv Rd) 1)
      ()
 )
-
+
 ; Arithmetic operations
 (dni addgrgr
      "ADD general register to general register"
@@ -1354,7 +1354,7 @@ 
      (set-psw Rd (index-of Rd) (sub Rd (add imm2 1)) 1)
      ()
 )
-
+
 ; Logical Shift
 (dni rrcgrgr
      "Rotate right general register by general register"
@@ -1475,7 +1475,7 @@ 
 			 1) 1)
      ()
 )
-
+
 ; Bitwise operations
 (dni set1grimm
      "Set bit in general register by immediate"
diff --git a/cpu/xstormy16.opc b/cpu/xstormy16.opc
index 6d2d16c1bb8..54cb9018e90 100644
--- a/cpu/xstormy16.opc
+++ b/cpu/xstormy16.opc
@@ -34,7 +34,7 @@ 
    <arch>-asm.c additions use: "-- asm.c"
    <arch>-dis.c additions use: "-- dis.c"
    <arch>-ibd.h additions use: "-- ibd.h".  */
-
+
 /* -- opc.h */
 
 /* Allows reason codes to be output when assembler errors occur.  */
@@ -45,7 +45,7 @@ 
 #define CGEN_DIS_HASH_SIZE 1
 #define CGEN_DIS_HASH(buf, value) 0
 /* -- */
-
+
 /* -- asm.c */
 
 /* The machine-independent code doesn't know how to disambiguate