[committed] hppa: Fix TARGET_SOFT_FLOAT patterns in pa.md

Message ID 98c1c4e3-91b5-1232-02d8-d8961415b1b1@bell.net
State New
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  • [committed] hppa: Fix TARGET_SOFT_FLOAT patterns in pa.md
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Commit Message

John David Anglin Oct. 14, 2021, 1:11 a.m.
This change fixes building libgcc with -msoft-float.  Getting soft float to work in libgcc
is still a work in progress.

Tested on hppa-unkown-linux-gnu, hppa2.0w-hp-hpux11.11 and hppa64-hp-hpux11.11.

Committed to active branches.

Dave
---
Fix TARGET_SOFT_FLOAT patterns in pa.md

2021-10-13  John David Anglin  <danglin@gcc.gnu.org>

gcc/ChangeLog:

	* config/pa/pa.md (cbranchsf4): Disable if TARGET_SOFT_FLOAT.
	(cbranchdf4): Likewise.
	Add missing move patterns for TARGET_SOFT_FLOAT.

Patch

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index b314f96de35..ba947ab1be9 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -1383,7 +1383,7 @@ 
                          (match_operand:SF 2 "reg_or_0_operand" "")])
  		      (label_ref (match_operand 3 "" ""))
  		      (pc)))]
-  ""
+  "! TARGET_SOFT_FLOAT"
    "
  {
    pa_emit_bcond_fp (operands);
@@ -1398,7 +1398,7 @@ 
                          (match_operand:DF 2 "reg_or_0_operand" "")])
  		      (label_ref (match_operand 3 "" ""))
  		      (pc)))]
-  ""
+  "! TARGET_SOFT_FLOAT"
    "
  {
    pa_emit_bcond_fp (operands);
@@ -2236,6 +2236,29 @@ 
     (set_attr "pa_combine_type" "addmove")
     (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])

+(define_insn ""
+  [(set (match_operand:SI 0 "move_dest_operand"
+			  "=r,r,r,r,r,r,Q,!*q,!r")
+	(match_operand:SI 1 "move_src_operand"
+			  "A,r,J,N,K,RQ,rM,!rM,!*q"))]
+  "(register_operand (operands[0], SImode)
+    || reg_or_0_operand (operands[1], SImode))
+   && TARGET_SOFT_FLOAT
+   && TARGET_64BIT"
+  "@
+   ldw RT'%A1,%0
+   copy %1,%0
+   ldi %1,%0
+   ldil L'%1,%0
+   {zdepi|depwi,z} %Z1,%0
+   ldw%M1 %1,%0
+   stw%M0 %r1,%0
+   mtsar %r1
+   {mfctl|mfctl,w} %%sar,%0"
+  [(set_attr "type" "load,move,move,move,shift,load,store,move,move")
+   (set_attr "pa_combine_type" "addmove")
+   (set_attr "length" "4,4,4,4,4,4,4,4,4")])
+
  (define_insn ""
    [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
  	(match_operand:SI 1 "register_operand" "f"))]
@@ -4042,6 +4065,25 @@ 
     (set_attr "pa_combine_type" "addmove")
     (set_attr "length" "4,4,4,4,4,4,4,4,4")])

+(define_insn ""
+  [(set (match_operand:DF 0 "move_dest_operand"
+			  "=!*r,*r,*r,*r,*r,Q")
+	(match_operand:DF 1 "move_src_operand"
+			  "!*r,J,N,K,RQ,*rG"))]
+  "(register_operand (operands[0], DFmode)
+    || reg_or_0_operand (operands[1], DFmode))
+   && TARGET_SOFT_FLOAT && TARGET_64BIT"
+  "@
+   copy %1,%0
+   ldi %1,%0
+   ldil L'%1,%0
+   depdi,z %z1,%0
+   ldd%M1 %1,%0
+   std%M0 %r1,%0"
+  [(set_attr "type" "move,move,move,shift,load,store")
+   (set_attr "pa_combine_type" "addmove")
+   (set_attr "length" "4,4,4,4,4,4")])
+
  
  (define_expand "movdi"
    [(set (match_operand:DI 0 "general_operand" "")
@@ -4200,6 +4242,28 @@ 
     (set_attr "pa_combine_type" "addmove")
     (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])

+(define_insn ""
+  [(set (match_operand:DI 0 "move_dest_operand"
+			  "=r,r,r,r,r,r,Q,!*q,!r")
+	(match_operand:DI 1 "move_src_operand"
+			  "A,r,J,N,K,RQ,rM,!rM,!*q"))]
+  "(register_operand (operands[0], DImode)
+    || reg_or_0_operand (operands[1], DImode))
+   && TARGET_SOFT_FLOAT && TARGET_64BIT"
+  "@
+   ldd RT'%A1,%0
+   copy %1,%0
+   ldi %1,%0
+   ldil L'%1,%0
+   depdi,z %z1,%0
+   ldd%M1 %1,%0
+   std%M0 %r1,%0
+   mtsar %r1
+   {mfctl|mfctl,w} %%sar,%0"
+  [(set_attr "type" "load,move,move,move,shift,load,store,move,move")
+   (set_attr "pa_combine_type" "addmove")
+   (set_attr "length" "4,4,4,4,4,4,4,4,4")])
+
  (define_insn ""
    [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
  	(match_operand:DI 1 "register_operand" "f"))]
@@ -4405,6 +4469,23 @@ 
     (set_attr "pa_combine_type" "addmove")
     (set_attr "length" "4,4,4,4,4,4")])

+(define_insn ""
+  [(set (match_operand:SF 0 "move_dest_operand"
+			  "=!*r,*r,Q")
+	(match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
+			  "!*rG,RQ,*rG"))]
+  "(register_operand (operands[0], SFmode)
+    || reg_or_0_operand (operands[1], SFmode))
+   && TARGET_SOFT_FLOAT
+   && TARGET_64BIT"
+  "@
+   copy %r1,%0
+   ldw%M1 %1,%0
+   stw%M0 %r1,%0"
+  [(set_attr "type" "move,load,store")
+   (set_attr "pa_combine_type" "addmove")
+   (set_attr "length" "4,4,4")])
+
  (define_insn ""
    [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
  	(match_operand:SF 1 "register_operand" "f"))]