bpf: correct zero_extend output templates

Message ID 20210909212743.11186-1-david.faust@oracle.com
State New
Headers show
Series
  • bpf: correct zero_extend output templates
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Commit Message

apinski--- via Gcc-patches Sept. 9, 2021, 9:27 p.m.
The output templates for zero_extendhidi2 and zero_extendqidi2 could
lead to incorrect code generation when zero-extending one register into
another. This patch adds a new output template to the define_insns to
handle such cases and produce correct asm.

gcc/ChangeLog:
	* config/bpf/bpf.md (zero_extendhidi2): Add new output template
	for register-to-register extensions.
	(zero_extendqidi2): Likewise.
---
 gcc/config/bpf/bpf.md | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

-- 
2.33.0

Comments

apinski--- via Gcc-patches Sept. 9, 2021, 10:48 p.m. | #1
Hi David.

> The output templates for zero_extendhidi2 and zero_extendqidi2 could

> lead to incorrect code generation when zero-extending one register into

> another. This patch adds a new output template to the define_insns to

> handle such cases and produce correct asm.

>

> gcc/ChangeLog:

> 	* config/bpf/bpf.md (zero_extendhidi2): Add new output template

> 	for register-to-register extensions.

> 	(zero_extendqidi2): Likewise.


This patch is OK.
Thanks.

> ---

>  gcc/config/bpf/bpf.md | 14 ++++++++------

>  1 file changed, 8 insertions(+), 6 deletions(-)

>

> diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md

> index 03830cc250e..c51add728ef 100644

> --- a/gcc/config/bpf/bpf.md

> +++ b/gcc/config/bpf/bpf.md

> @@ -241,22 +241,24 @@

>  ;; the ldx{bhwdw} instructions to load the values in registers.

>  

>  (define_insn "zero_extendhidi2"

> -  [(set (match_operand:DI 0 "register_operand" "=r,r")

> -	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]

> +  [(set (match_operand:DI 0 "register_operand" "=r,r,r")

> +	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "0,r,m")))]

>    ""

>    "@

>     and\t%0,0xffff

> +   mov\t%0,%1\;and\t%0,0xffff

>     ldxh\t%0,%1"

> -  [(set_attr "type" "alu,ldx")])

> +  [(set_attr "type" "alu,alu,ldx")])

>  

>  (define_insn "zero_extendqidi2"

> -  [(set (match_operand:DI 0 "register_operand" "=r,r")

> -	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]

> +  [(set (match_operand:DI 0 "register_operand" "=r,r,r")

> +	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "0,r,m")))]

>    ""

>    "@

>     and\t%0,0xff

> +   mov\t%0,%1\;and\t%0,0xff

>     ldxb\t%0,%1"

> -  [(set_attr "type" "alu,ldx")])

> +  [(set_attr "type" "alu,alu,ldx")])

>  

>  (define_insn "zero_extendsidi2"

>    [(set (match_operand:DI 0 "register_operand" "=r,r")

Patch

diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md
index 03830cc250e..c51add728ef 100644
--- a/gcc/config/bpf/bpf.md
+++ b/gcc/config/bpf/bpf.md
@@ -241,22 +241,24 @@ 
 ;; the ldx{bhwdw} instructions to load the values in registers.
 
 (define_insn "zero_extendhidi2"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "0,r,m")))]
   ""
   "@
    and\t%0,0xffff
+   mov\t%0,%1\;and\t%0,0xffff
    ldxh\t%0,%1"
-  [(set_attr "type" "alu,ldx")])
+  [(set_attr "type" "alu,alu,ldx")])
 
 (define_insn "zero_extendqidi2"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
+  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "0,r,m")))]
   ""
   "@
    and\t%0,0xff
+   mov\t%0,%1\;and\t%0,0xff
    ldxb\t%0,%1"
-  [(set_attr "type" "alu,ldx")])
+  [(set_attr "type" "alu,alu,ldx")])
 
 (define_insn "zero_extendsidi2"
   [(set (match_operand:DI 0 "register_operand" "=r,r")