[v2] x86: Don't return hard register when LRA is in progress

Message ID 20210723024125.1297782-1-hjl.tools@gmail.com
State New
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Series
  • [v2] x86: Don't return hard register when LRA is in progress
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Commit Message

Ian Lance Taylor via Gcc-patches July 23, 2021, 2:41 a.m.
Don't return hard register in ix86_gen_scratch_sse_rtx when LRA is in
progress to avoid ICE when there are no available hard registers for
LRA.

gcc/

	PR target/101504
	* config/i386/i386.c (ix86_gen_scratch_sse_rtx): Don't return
	hard register when LRA is in progress.

gcc/testsuite/

	PR target/101504
	* gcc.target/i386/pr101504.c: New test.
---
 gcc/config/i386/i386.c                   |  2 +-
 gcc/testsuite/gcc.target/i386/pr101504.c | 23 +++++++++++++++++++++++
 2 files changed, 24 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr101504.c

-- 
2.31.1

Comments

Ian Lance Taylor via Gcc-patches July 23, 2021, 4:56 a.m. | #1
On Fri, Jul 23, 2021 at 10:41 AM H.J. Lu via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>

> Don't return hard register in ix86_gen_scratch_sse_rtx when LRA is in

> progress to avoid ICE when there are no available hard registers for

> LRA.

>

LGTM.
> gcc/

>

>         PR target/101504

>         * config/i386/i386.c (ix86_gen_scratch_sse_rtx): Don't return

>         hard register when LRA is in progress.

>

> gcc/testsuite/

>

>         PR target/101504

>         * gcc.target/i386/pr101504.c: New test.

> ---

>  gcc/config/i386/i386.c                   |  2 +-

>  gcc/testsuite/gcc.target/i386/pr101504.c | 23 +++++++++++++++++++++++

>  2 files changed, 24 insertions(+), 1 deletion(-)

>  create mode 100644 gcc/testsuite/gcc.target/i386/pr101504.c

>

> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c

> index ff96134fb37..876a19f4c1f 100644

> --- a/gcc/config/i386/i386.c

> +++ b/gcc/config/i386/i386.c

> @@ -23180,7 +23180,7 @@ ix86_optab_supported_p (int op, machine_mode mode1, machine_mode,

>  rtx

>  ix86_gen_scratch_sse_rtx (machine_mode mode)

>  {

> -  if (TARGET_SSE)

> +  if (TARGET_SSE && !lra_in_progress)

>      return gen_rtx_REG (mode, (TARGET_64BIT

>                                ? LAST_REX_SSE_REG

>                                : LAST_SSE_REG));

> diff --git a/gcc/testsuite/gcc.target/i386/pr101504.c b/gcc/testsuite/gcc.target/i386/pr101504.c

> new file mode 100644

> index 00000000000..2ad0405dd7b

> --- /dev/null

> +++ b/gcc/testsuite/gcc.target/i386/pr101504.c

> @@ -0,0 +1,23 @@

> +/* { dg-do compile } */

> +/* { dg-options "-O2 -march=skylake" } */

> +

> +typedef unsigned int __attribute__((__vector_size__ (32))) U;

> +typedef unsigned char __attribute__((__vector_size__ (64))) V;

> +

> +V g;

> +

> +U

> +foo (void)

> +{

> +  V v = __builtin_shufflevector (g, g,

> +                                0, 1, 2, 0, 5, 1, 0, 1, 3, 2, 3, 0, 4, 3, 1, 2,

> +                                2, 0, 4, 2, 3, 1, 1, 2, 3, 4, 1, 1, 0, 0, 5, 2,

> +                                0, 3, 3, 3, 3, 4, 5, 0, 1, 5, 2, 1, 0, 1, 1, 2,

> +                                3, 2, 0, 5, 4, 5, 1, 0, 1, 4, 4, 3, 4, 5, 2, 0);

> +  v ^= 255;

> +  V w = v + g;

> +  U u = ((union { V a; U b; }) w).b + ((union { V a; U b; }) w).b[1];

> +  return u;

> +}

> +

> +/* { dg-final { scan-assembler-not "\.byte\[ \t\]+-1\n" } } */

> --

> 2.31.1

>



-- 
BR,
Hongtao

Patch

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index ff96134fb37..876a19f4c1f 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -23180,7 +23180,7 @@  ix86_optab_supported_p (int op, machine_mode mode1, machine_mode,
 rtx
 ix86_gen_scratch_sse_rtx (machine_mode mode)
 {
-  if (TARGET_SSE)
+  if (TARGET_SSE && !lra_in_progress)
     return gen_rtx_REG (mode, (TARGET_64BIT
 			       ? LAST_REX_SSE_REG
 			       : LAST_SSE_REG));
diff --git a/gcc/testsuite/gcc.target/i386/pr101504.c b/gcc/testsuite/gcc.target/i386/pr101504.c
new file mode 100644
index 00000000000..2ad0405dd7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr101504.c
@@ -0,0 +1,23 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=skylake" } */
+
+typedef unsigned int __attribute__((__vector_size__ (32))) U;
+typedef unsigned char __attribute__((__vector_size__ (64))) V;
+
+V g;
+
+U
+foo (void)
+{
+  V v = __builtin_shufflevector (g, g,
+				 0, 1, 2, 0, 5, 1, 0, 1, 3, 2, 3, 0, 4, 3, 1, 2,
+				 2, 0, 4, 2, 3, 1, 1, 2, 3, 4, 1, 1, 0, 0, 5, 2,
+				 0, 3, 3, 3, 3, 4, 5, 0, 1, 5, 2, 1, 0, 1, 1, 2,
+				 3, 2, 0, 5, 4, 5, 1, 0, 1, 4, 4, 3, 4, 5, 2, 0);
+  v ^= 255;
+  V w = v + g;
+  U u = ((union { V a; U b; }) w).b + ((union { V a; U b; }) w).b[1];
+  return u;
+}
+
+/* { dg-final { scan-assembler-not "\.byte\[ \t\]+-1\n" } } */