[integration,3/4] RISC-V/rvv: Changed assembler mnemonic for unordered floating-point reductions.

Message ID 20210621062703.8369-4-nelson.chu@sifive.com
State New
Headers show
Series
  • RISC-V/rvv: Update rvv from v01.0 to v1.0 except zve feature.
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Commit Message

Nelson Chu June 21, 2021, 6:27 a.m.
Changed from vfredsum and vfwredsum to vfredusum and vfwredusum respectively.
Older names kept as aliases.

gas/
    * testsuite/gas/riscv/extended/vector-insns.d: Updated.
    * testsuite/gas/riscv/extended/vector-insns.s: Likewise.
include/
    * opcode/riscv-opc-extended.h: Updated.
opcodes/
    * riscv-opc.c (riscv_draft_opcodes): Added vfredusum.vs and vfwredusum.vs.
    Marked the old vfredusum.vs and vfwredsum.vs as their aliases.
---
 gas/testsuite/gas/riscv/extended/vector-insns.d | 12 ++++++++----
 gas/testsuite/gas/riscv/extended/vector-insns.s | 12 ++++++++----
 include/opcode/riscv-opc-extended.h             |  8 ++++----
 opcodes/riscv-opc.c                             |  6 ++++--
 4 files changed, 24 insertions(+), 14 deletions(-)

-- 
2.30.2

Patch

diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.d b/gas/testsuite/gas/riscv/extended/vector-insns.d
index 6d77f936291..c8c01c9d49d 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns.d
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.d
@@ -1869,17 +1869,21 @@  Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+c0860257[ 	]+vwredsumu.vs[ 	]+v4,v8,v12,v0.t
 [ 	]+[0-9a-f]+:[ 	]+c4860257[ 	]+vwredsum.vs[ 	]+v4,v8,v12,v0.t
 [ 	]+[0-9a-f]+:[ 	]+0e861257[ 	]+vfredosum.vs[ 	]+v4,v8,v12
-[ 	]+[0-9a-f]+:[ 	]+06861257[ 	]+vfredsum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+06861257[ 	]+vfredusum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+06861257[ 	]+vfredusum.vs[ 	]+v4,v8,v12
 [ 	]+[0-9a-f]+:[ 	]+1e861257[ 	]+vfredmax.vs[ 	]+v4,v8,v12
 [ 	]+[0-9a-f]+:[ 	]+16861257[ 	]+vfredmin.vs[ 	]+v4,v8,v12
 [ 	]+[0-9a-f]+:[ 	]+0c861257[ 	]+vfredosum.vs[ 	]+v4,v8,v12,v0.t
-[ 	]+[0-9a-f]+:[ 	]+04861257[ 	]+vfredsum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+04861257[ 	]+vfredusum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+04861257[ 	]+vfredusum.vs[ 	]+v4,v8,v12,v0.t
 [ 	]+[0-9a-f]+:[ 	]+1c861257[ 	]+vfredmax.vs[ 	]+v4,v8,v12,v0.t
 [ 	]+[0-9a-f]+:[ 	]+14861257[ 	]+vfredmin.vs[ 	]+v4,v8,v12,v0.t
 [ 	]+[0-9a-f]+:[ 	]+ce861257[ 	]+vfwredosum.vs[ 	]+v4,v8,v12
-[ 	]+[0-9a-f]+:[ 	]+c6861257[ 	]+vfwredsum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c6861257[ 	]+vfwredusum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c6861257[ 	]+vfwredusum.vs[ 	]+v4,v8,v12
 [ 	]+[0-9a-f]+:[ 	]+cc861257[ 	]+vfwredosum.vs[ 	]+v4,v8,v12,v0.t
-[ 	]+[0-9a-f]+:[ 	]+c4861257[ 	]+vfwredsum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c4861257[ 	]+vfwredusum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c4861257[ 	]+vfwredusum.vs[ 	]+v4,v8,v12,v0.t
 [ 	]+[0-9a-f]+:[ 	]+66842257[ 	]+vmmv.m[ 	]+v4,v8
 [ 	]+[0-9a-f]+:[ 	]+66842257[ 	]+vmmv.m[ 	]+v4,v8
 [ 	]+[0-9a-f]+:[ 	]+6e422257[ 	]+vmclr.m[ 	]+v4
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.s b/gas/testsuite/gas/riscv/extended/vector-insns.s
index 3e45b9d963b..bace7abbf01 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns.s
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.s
@@ -2096,18 +2096,22 @@ 
 	vwredsum.vs v4, v8, v12, v0.t
 
 	vfredosum.vs v4, v8, v12
-	vfredsum.vs v4, v8, v12
+	vfredusum.vs v4, v8, v12
+	vfredsum.vs v4, v8, v12		# Alias of vfredusum.vs.
 	vfredmax.vs v4, v8, v12
 	vfredmin.vs v4, v8, v12
 	vfredosum.vs v4, v8, v12, v0.t
-	vfredsum.vs v4, v8, v12, v0.t
+	vfredusum.vs v4, v8, v12, v0.t
+	vfredsum.vs v4, v8, v12, v0.t	# Alias of vfredusum.vs.
 	vfredmax.vs v4, v8, v12, v0.t
 	vfredmin.vs v4, v8, v12, v0.t
 
 	vfwredosum.vs v4, v8, v12
-	vfwredsum.vs v4, v8, v12
+	vfwredusum.vs v4, v8, v12
+	vfwredsum.vs v4, v8, v12	# Alias of vfwredusum.vs.
 	vfwredosum.vs v4, v8, v12, v0.t
-	vfwredsum.vs v4, v8, v12, v0.t
+	vfwredusum.vs v4, v8, v12, v0.t
+	vfwredsum.vs v4, v8, v12, v0.t	# Alias of vfwredusum.vs.
 
 	# Aliases
 	vmcpy.m v4, v8
diff --git a/include/opcode/riscv-opc-extended.h b/include/opcode/riscv-opc-extended.h
index 9d509b318b2..907313a5a72 100644
--- a/include/opcode/riscv-opc-extended.h
+++ b/include/opcode/riscv-opc-extended.h
@@ -1359,16 +1359,16 @@ 
 #define MASK_VWREDSUMVS		0xfc00707f
 #define MATCH_VFREDOSUMVS	0x0c001057
 #define MASK_VFREDOSUMVS	0xfc00707f
-#define MATCH_VFREDSUMVS	0x04001057
-#define MASK_VFREDSUMVS		0xfc00707f
+#define MATCH_VFREDUSUMVS	0x04001057
+#define MASK_VFREDUSUMVS	0xfc00707f
 #define MATCH_VFREDMAXVS	0x1c001057
 #define MASK_VFREDMAXVS		0xfc00707f
 #define MATCH_VFREDMINVS	0x14001057
 #define MASK_VFREDMINVS		0xfc00707f
 #define MATCH_VFWREDOSUMVS	0xcc001057
 #define MASK_VFWREDOSUMVS	0xfc00707f
-#define MATCH_VFWREDSUMVS	0xc4001057
-#define MASK_VFWREDSUMVS	0xfc00707f
+#define MATCH_VFWREDUSUMVS	0xc4001057
+#define MASK_VFWREDUSUMVS	0xfc00707f
 #define MATCH_VMANDMM		0x66002057
 #define MASK_VMANDMM		0xfe00707f
 #define MATCH_VMNANDMM		0x76002057
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 98736072388..be5d49ee33e 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2153,12 +2153,14 @@  const struct riscv_opcode riscv_draft_opcodes[] =
 {"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
 
 {"vfredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
-{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, 0},
+{"vfredusum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, 0},
+{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, INSN_ALIAS},
 {"vfredmax.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
 {"vfredmin.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
 
 {"vfwredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
-{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, 0},
+{"vfwredusum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, 0},
+{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, INSN_ALIAS},
 
 {"vmmv.m",     0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
 {"vmcpy.m",    0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},