[integration,2/4] RISC-V/rvv: Changed assembler mnemonic for mask loads/stores.

Message ID 20210621062703.8369-3-nelson.chu@sifive.com
State New
Headers show
Series
  • RISC-V/rvv: Update rvv from v01.0 to v1.0 except zve feature.
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Commit Message

Nelson Chu June 21, 2021, 6:27 a.m.
Changed from vle1.v to vlm.v, and vse1.v to vsm.v.
Older names kept as aliases.

gas/
    * testsuite/gas/riscv/extended/vector-insns.d: Updated.
    * testsuite/gas/riscv/extended/vector-insns.s: Likewise.
include/
    * opcode/riscv-opc-extended.h: Updated.
opcodes/
    * riscv-opc.c (riscv_draft_opcodes): Added vlm.v and vsm.v.
---
 gas/testsuite/gas/riscv/extended/vector-insns.d | 12 ++++++++----
 gas/testsuite/gas/riscv/extended/vector-insns.s |  8 ++++++--
 include/opcode/riscv-opc-extended.h             |  8 ++++----
 opcodes/riscv-opc.c                             |  6 ++++--
 4 files changed, 22 insertions(+), 12 deletions(-)

-- 
2.30.2

Patch

diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.d b/gas/testsuite/gas/riscv/extended/vector-insns.d
index f8a254d49b1..6d77f936291 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns.d
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.d
@@ -44,10 +44,14 @@  Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+ca95f557[ 	]+vsetivli[ 	]+a0,11,e256,m2,tu,ma
 [ 	]+[0-9a-f]+:[ 	]+c695f557[ 	]+vsetivli[ 	]+a0,11,e256,m2,ta,mu
 [ 	]+[0-9a-f]+:[ 	]+c295f557[ 	]+vsetivli[ 	]+a0,11,e256,m2,tu,mu
-[ 	]+[0-9a-f]+:[ 	]+02b50207[ 	]+vle1.v[ 	]+v4,\(a0\)
-[ 	]+[0-9a-f]+:[ 	]+02b50207[ 	]+vle1.v[ 	]+v4,\(a0\)
-[ 	]+[0-9a-f]+:[ 	]+02b50227[ 	]+vse1.v[ 	]+v4,\(a0\)
-[ 	]+[0-9a-f]+:[ 	]+02b50227[ 	]+vse1.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02b50207[ 	]+vlm.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02b50207[ 	]+vlm.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02b50207[ 	]+vlm.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02b50207[ 	]+vlm.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02b50227[ 	]+vsm.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02b50227[ 	]+vsm.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02b50227[ 	]+vsm.v[ 	]+v4,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+02b50227[ 	]+vsm.v[ 	]+v4,\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+02050207[ 	]+vle8.v[ 	]+v4,\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+02050207[ 	]+vle8.v[ 	]+v4,\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+00050207[ 	]+vle8.v[ 	]+v4,\(a0\),v0.t
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.s b/gas/testsuite/gas/riscv/extended/vector-insns.s
index 380e0441c99..3e45b9d963b 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns.s
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.s
@@ -36,9 +36,13 @@ 
 	vsetivli a0, 0xb, e256, m2, ta, mu
 	vsetivli a0, 0xb, e256, m2, tu, mu
 
-	vle1.v v4, (a0)
+	vlm.v v4, (a0)
+	vlm.v v4, 0(a0)
+	vle1.v v4, (a0)		# Alias of vlm.v
 	vle1.v v4, 0(a0)
-	vse1.v v4, (a0)
+	vsm.v v4, (a0)
+	vsm.v v4, 0(a0)
+	vse1.v v4, (a0)		# Alias of vsm.v
 	vse1.v v4, 0(a0)
 
 	vle8.v v4, (a0)
diff --git a/include/opcode/riscv-opc-extended.h b/include/opcode/riscv-opc-extended.h
index 72fcaf4bbc5..9d509b318b2 100644
--- a/include/opcode/riscv-opc-extended.h
+++ b/include/opcode/riscv-opc-extended.h
@@ -99,10 +99,10 @@ 
 #define MASK_VSETIVLI		0xc000707f
 #define MATCH_VSETVLI		0x00007057
 #define MASK_VSETVLI		0x8000707f
-#define MATCH_VLE1V		0x02b00007
-#define MASK_VLE1V		0xfff0707f
-#define MATCH_VSE1V		0x02b00027
-#define MASK_VSE1V		0xfff0707f
+#define MATCH_VLMV		0x02b00007
+#define MASK_VLMV		0xfff0707f
+#define MATCH_VSMV		0x02b00027
+#define MASK_VSMV		0xfff0707f
 #define MATCH_VLE8V		0x00000007
 #define MASK_VLE8V		0xfdf0707f
 #define MATCH_VLE16V		0x00005007
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index e6c284ca59b..98736072388 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1417,8 +1417,10 @@  const struct riscv_opcode riscv_draft_opcodes[] =
 {"vsetvli",    0, INSN_CLASS_V,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
 {"vsetivli",   0, INSN_CLASS_V,  "d,Z,Vb", MATCH_VSETIVLI, MASK_VSETIVLI, match_opcode, 0},
 
-{"vle1.v",     0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VLE1V, MASK_VLE1V, match_opcode, INSN_DREF },
-{"vse1.v",     0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VSE1V, MASK_VSE1V, match_opcode, INSN_DREF },
+{"vlm.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VLMV, MASK_VLMV, match_opcode, INSN_DREF },
+{"vsm.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VSMV, MASK_VSMV, match_opcode, INSN_DREF },
+{"vle1.v",     0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VLMV, MASK_VLMV, match_opcode, INSN_DREF|INSN_ALIAS },
+{"vse1.v",     0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VSMV, MASK_VSMV, match_opcode, INSN_DREF|INSN_ALIAS },
 
 {"vle8.v",     0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_vd_neq_vm, INSN_DREF },
 {"vle16.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_vd_neq_vm, INSN_DREF },