[integration,1/4] RISC-V/rvv: Added assembly pseudoinstructions, vfabs.v.

Message ID 20210621062703.8369-2-nelson.chu@sifive.com
State New
Headers show
Series
  • RISC-V/rvv: Update rvv from v01.0 to v1.0 except zve feature.
Related show

Commit Message

Nelson Chu June 21, 2021, 6:27 a.m.
vfabs.v vd,vs = vfsgnjx.vv vd,vs,vs

gas/
    * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l: Updated.
    * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s: Likewise.
    * testsuite/gas/riscv/extended/vector-insns.d: Likewise.
    * testsuite/gas/riscv/extended/vector-insns.s: Likewise.
opcodes/
    * riscv-opc.c: Added vfabs.v as an alias of vfsgnjx.vv.
---
 .../gas/riscv/extended/vector-insns-fail-arith-floatp.l         | 1 +
 .../gas/riscv/extended/vector-insns-fail-arith-floatp.s         | 2 ++
 gas/testsuite/gas/riscv/extended/vector-insns.d                 | 2 ++
 gas/testsuite/gas/riscv/extended/vector-insns.s                 | 2 ++
 opcodes/riscv-opc.c                                             | 1 +
 5 files changed, 8 insertions(+)

-- 
2.30.2

Patch

diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l
index bcc49a09080..9900dbb1e58 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l
@@ -34,6 +34,7 @@ 
 .*Error: illegal operands vd cannot overlap vm `vfmax.vv v0,v4,v8,v0.t'
 .*Error: illegal operands vd cannot overlap vm `vfmax.vf v0,v4,fa1,v0.t'
 .*Error: illegal operands vd cannot overlap vm `vfneg.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfabs.v v0,v4,v0.t'
 .*Error: illegal operands vd cannot overlap vm `vfsgnj.vv v0,v4,v8,v0.t'
 .*Error: illegal operands vd cannot overlap vm `vfsgnj.vf v0,v4,fa1,v0.t'
 .*Error: illegal operands vd cannot overlap vm `vfsgnjn.vv v0,v4,v8,v0.t'
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s
index a48b1a3fd33..19ed26a95aa 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s
@@ -120,6 +120,8 @@ 
 
 	vfneg.v v4, v4			# OK
 	vfneg.v v0, v4, v0.t		# vd overlap vm
+	vfabs.v v4, v4			# OK
+	vfabs.v v0, v4, v0.t		# vd overlap vm
 
 	vfsgnj.vv v4, v4, v8		# OK
 	vfsgnj.vv v8, v4, v8		# OK
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.d b/gas/testsuite/gas/riscv/extended/vector-insns.d
index 01770c48bdd..f8a254d49b1 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns.d
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.d
@@ -1762,6 +1762,8 @@  Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+18865257[ 	]+vfmax.vf[ 	]+v4,v8,fa2,v0.t
 [ 	]+[0-9a-f]+:[ 	]+26841257[ 	]+vfneg.v[ 	]+v4,v8
 [ 	]+[0-9a-f]+:[ 	]+24841257[ 	]+vfneg.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+2a841257[ 	]+vfabs.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+28841257[ 	]+vfabs.v[ 	]+v4,v8,v0.t
 [ 	]+[0-9a-f]+:[ 	]+22861257[ 	]+vfsgnj.vv[ 	]+v4,v8,v12
 [ 	]+[0-9a-f]+:[ 	]+22865257[ 	]+vfsgnj.vf[ 	]+v4,v8,fa2
 [ 	]+[0-9a-f]+:[ 	]+26861257[ 	]+vfsgnjn.vv[ 	]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.s b/gas/testsuite/gas/riscv/extended/vector-insns.s
index 5c78e28e776..380e0441c99 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns.s
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.s
@@ -1978,6 +1978,8 @@ 
 
 	vfneg.v v4, v8
 	vfneg.v v4, v8, v0.t
+	vfabs.v v4, v8
+	vfabs.v v4, v8, v0.t
 
 	vfsgnj.vv v4, v8, v12
 	vfsgnj.vf v4, v8, fa2
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index ca6c0d02458..e6c284ca59b 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2087,6 +2087,7 @@  const struct riscv_opcode riscv_draft_opcodes[] =
 {"vfmax.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_vd_neq_vm, 0},
 
 {"vfneg.v",    0, INSN_CLASS_V_AND_F, "Vd,VuVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vs1_eq_vs2_neq_vm, INSN_ALIAS },
+{"vfabs.v",    0, INSN_CLASS_V_AND_F, "Vd,VuVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vs1_eq_vs2_neq_vm, INSN_ALIAS },
 
 {"vfsgnj.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_vd_neq_vm, 0},
 {"vfsgnj.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_vd_neq_vm, 0},