[committed,13/18] MIPS/opcodes: Remove DMFC3 and DMTC3 instructions

Message ID alpine.DEB.2.21.2105280034080.11113@angie.orcam.me.uk
State New
Headers show
Series
  • MIPS coprocessor opcodes handling fixes
Related show

Commit Message

Maciej W. Rozycki May 29, 2021, 1:37 a.m.
Coprocessor 3 has been removed from the MIPS ISA as from MIPS III[1][2] 
with the LDC3 and SDC3 instructions having been replaced with LD and SD 
instructions respectively and therefore the doubleword move instructions 
from and to that coprocessor have never materialized (for 32-bit ISAs 
coprocessor 3 has likewise been removed as from MIPS32r2[3]).  Remove 
the DMFC3 and DMTC3 instructions from the opcode table then to avoid 
confusion.

References:

[1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., 
    Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3 
    and CP3 load/store", p. A-176

[2] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture", 
    p. A-179

[3] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, 
    Revision 2.00, June 9, 2003, Table A-2 "MIPS32 Encoding of the
    Opcode Field", p. 317

	opcodes/
	* mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3" 
	entries and associated comments.
---
 opcodes/mips-opc.c |    4 ----
 1 file changed, 4 deletions(-)

binutils-mips-opcodes-dmxc3-remove.diff

Patch

Index: binutils-gdb/opcodes/mips-opc.c
===================================================================
--- binutils-gdb.orig/opcodes/mips-opc.c
+++ binutils-gdb/opcodes/mips-opc.c
@@ -1112,8 +1112,6 @@  const struct mips_opcode mips_builtin_op
 {"dmtc1",		"t,G",		0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D,     0,		I3,		0,	SF },
 /* dmfc2 is at the bottom of the table.  */
 /* dmtc2 is at the bottom of the table.  */
-/* dmfc3 is at the bottom of the table.  */
-/* dmtc3 is at the bottom of the table.  */
 {"dmuh",		"d,s,t",	0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I69,		0,	0 },
 {"dmul",		"d,s,t",	0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I69,		0,	0 },
 {"dmul",		"d,v,t",	0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,	0,		IOCT,		0,	0 },
@@ -2161,8 +2159,6 @@  const struct mips_opcode mips_builtin_op
 {"bc3tl",		"p",		0x4d030000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"cfc3",		"t,g",		0x4c400000, 0xffe007ff,	WR_1|RD_C3|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"ctc3",		"t,g",		0x4cc00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
-{"dmfc3",		"t,G",		0x4c200000, 0xffe007ff,	WR_1|RD_C3|LC,		0,		I3,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
-{"dmtc3",		"t,G",		0x4ca00000, 0xffe007ff,	RD_1|WR_C3|WR_CC|CM,	0,		I3,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"mfc3",		"t,G",		0x4c000000, 0xffe007ff,	WR_1|RD_C3|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"mfc3",		"t,G,H",	0x4c000000, 0xffe007f8,	WR_1|RD_C3|LC,		0,		I32,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"mtc3",		"t,G",		0x4c800000, 0xffe007ff,	RD_1|WR_C3|WR_CC|CM,	0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },