[committed,06/18] MIPS/opcodes: Do not use CP0 register names for control registers

Message ID alpine.DEB.2.21.2105271753370.11113@angie.orcam.me.uk
State New
Headers show
Series
  • MIPS coprocessor opcodes handling fixes
Related show

Commit Message

Maciej W. Rozycki May 29, 2021, 1:37 a.m.
The CP0 control register set has never been defined, however encodings 
for the CFC0 and CTC0 instructions remained available for implementers 
up until the MIPS32 ISA declared them invalid and causing the Reserved 
Instruction exception[1].  Therefore we handle them for both assembly 
and disassembly, however in the latter case the names of CP0 registers 
from the regular set are incorrectly printed if named registers are 
requested.  This is because we do not define separate operand classes 
for coprocessor regular and control registers respectively, which means 
the disassembler has no way to tell the two cases apart.  Consequently 
nonsensical disassembly is produced like:

	cfc0	v0,c0_random

Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0 
instructions[2] although it failed to document them in the relevant 
opcode table until MIPSr6 only.

Correct the issue then by defining a new register class, OP_REG_CONTROL, 
and corresponding operand codes, `g' and `y' for the two positions in 
the machine instruction a control register operand can take.  Adjust the 
test cases affected accordingly.

While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries 
with each other so that they come in the alphabetical order.

References:

[1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
    Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of 
    rs Field", p. 242

[2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
    Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of 
    Instructions", pp. 195, 216

	include/
	* opcode/mips.h: Document `g' and `y' operand codes.
	(mips_reg_operand_type): Add OP_REG_CONTROL enumeration 
	constant.

	gas/
	* tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case.
	(macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G' 
	operand code.

	opcodes/
	* mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register 
	handling code over to...
	<OP_REG_CONTROL>: ... this new case.
	* mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
	(mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
	"cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries 
	replacing the `G' operand code with `g'.  Update "cftc1" and
	"cftc2" entries replacing the `E' operand code with `y'.
	* micromips-opc.c (decode_micromips_operand) <'g'>: New case.
	(micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" 
	entries replacing the `G' operand code with `g'.

	binutils/
	* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 
	operand disassembly.
	* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
---
 binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d |    2 -
 binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d |    2 -
 gas/config/tc-mips.c                                   |    9 +++--
 include/opcode/mips.h                                  |   11 +++++--
 opcodes/micromips-opc.c                                |    9 +++--
 opcodes/mips-dis.c                                     |    7 +++-
 opcodes/mips-opc.c                                     |   26 +++++++++--------
 7 files changed, 41 insertions(+), 25 deletions(-)

binutils-mips-opcodes-control.diff

Patch

Index: binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d
===================================================================
--- binutils-gdb.orig/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d
+++ binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d
@@ -7,7 +7,7 @@ 
 
 Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 40020800 	mfc0	v0,c0_random
-[0-9a-f]+ <[^>]*> 40420800 	cfc0	v0,c0_random
+[0-9a-f]+ <[^>]*> 40420800 	cfc0	v0,\$1
 [0-9a-f]+ <[^>]*> 40620800 	0x40620800
 [0-9a-f]+ <[^>]*> 40620c00 	0x40620c00
 	\.\.\.
Index: binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d
===================================================================
--- binutils-gdb.orig/binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d
+++ binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-3.d
@@ -7,7 +7,7 @@ 
 
 Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 40020800 	mfc0	v0,c0_random
-[0-9a-f]+ <[^>]*> 40420800 	cfc0	v0,c0_random
+[0-9a-f]+ <[^>]*> 40420800 	cfc0	v0,\$1
 [0-9a-f]+ <[^>]*> 40620800 	mfgc0	v0,c0_random
 [0-9a-f]+ <[^>]*> 40620c00 	0x40620c00
 	\.\.\.
Index: binutils-gdb/gas/config/tc-mips.c
===================================================================
--- binutils-gdb.orig/gas/config/tc-mips.c
+++ binutils-gdb/gas/config/tc-mips.c
@@ -5050,6 +5050,7 @@  convert_reg_type (const struct mips_opco
       return RTYPE_ACC;
 
     case OP_REG_COPRO:
+    case OP_REG_CONTROL:
       if (opcode->name[strlen (opcode->name) - 1] == '0')
 	return RTYPE_NUM | RTYPE_CP0;
       return RTYPE_NUM;
@@ -13837,18 +13838,18 @@  macro (struct mips_cl_insn *ip, char *st
        * or is there a reason for it?
        */
       start_noreorder ();
-      macro_build (NULL, "cfc1", "t,G", op[2], FCSR);
-      macro_build (NULL, "cfc1", "t,G", op[2], FCSR);
+      macro_build (NULL, "cfc1", "t,g", op[2], FCSR);
+      macro_build (NULL, "cfc1", "t,g", op[2], FCSR);
       macro_build (NULL, "nop", "");
       expr1.X_add_number = 3;
       macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
       expr1.X_add_number = 2;
       macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
-      macro_build (NULL, "ctc1", "t,G", AT, FCSR);
+      macro_build (NULL, "ctc1", "t,g", AT, FCSR);
       macro_build (NULL, "nop", "");
       macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
 		   op[0], op[1]);
-      macro_build (NULL, "ctc1", "t,G", op[2], FCSR);
+      macro_build (NULL, "ctc1", "t,g", op[2], FCSR);
       macro_build (NULL, "nop", "");
       end_noreorder ();
       break;
Index: binutils-gdb/include/opcode/mips.h
===================================================================
--- binutils-gdb.orig/include/opcode/mips.h
+++ binutils-gdb/include/opcode/mips.h
@@ -461,6 +461,10 @@  enum mips_reg_operand_type {
      also be used in some contexts.  */
   OP_REG_COPRO,
 
+  /* Coprocessor control registers $0-$31.  Mnemonic names like c1_fcsr can
+     also be used in some contexts.  */
+  OP_REG_CONTROL,
+
   /* Hardware registers $0-$31.  Mnemonic names like hwr_cpunum can
      also be used in some contexts.  */
   OP_REG_HW,
@@ -841,6 +845,7 @@  mips_opcode_32bit_p (const struct mips_o
    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
    "P" 5 bit performance-monitor register (OP_*_PERFREG)
    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
+   "g" 5 bit control destination register (OP_*_RD)
    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 
    Macro instructions:
@@ -899,6 +904,7 @@  mips_opcode_32bit_p (const struct mips_o
    "$" 1 bit load high flag (OP_*_MT_H)
    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
+   "y" 5 bit control target register (OP_*_RT)
    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
 
    MCU ASE usage:
@@ -1000,7 +1006,7 @@  mips_opcode_32bit_p (const struct mips_o
    "1234567890"
    "%[]<>(),+-:'@!#$*&\~"
    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
-   "abcdef hijkl  opqrstuvwx z"
+   "abcdef hijkl  opqrstuvwxyz"
 
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:
@@ -2277,6 +2283,7 @@  extern const int bfd_mips16_num_opcodes;
    "E" 5-bit target register (MICROMIPSOP_*_RT)
    "G" 5-bit source register (MICROMIPSOP_*_RS)
    "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
+   "g" 5-bit control source register (MICROMIPSOP_*_RS)
 
    Macro instructions:
    "A" general 32 bit expression
@@ -2338,7 +2345,7 @@  extern const int bfd_mips16_num_opcodes;
    "12345678 0"
    "<>(),+-.@\^|~"
    "ABCDEFGHI KLMN   RST V    "
-   "abcd f hijklmnopqrstuvw yz"
+   "abcd fghijklmnopqrstuvw yz"
 
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:
Index: binutils-gdb/opcodes/micromips-opc.c
===================================================================
--- binutils-gdb.orig/opcodes/micromips-opc.c
+++ binutils-gdb/opcodes/micromips-opc.c
@@ -176,6 +176,7 @@  decode_micromips_operand (const char *p)
     case 'b': REG (5, 16, GP);
     case 'c': HINT (10, 16);
     case 'd': REG (5, 11, GP);
+    case 'g': REG (5, 16, CONTROL);
     case 'h': HINT (5, 11);
     case 'i': HINT (16, 0);
     case 'j': SINT (16, 0);
@@ -548,15 +549,15 @@  const struct mips_opcode micromips_opcod
 {"ceil.l.s",		"T,S",		0x5400133b, 0xfc00ffff,	WR_1|RD_2|FP_S|FP_D,	0,		I1,		0,	0 },
 {"ceil.w.d",		"T,S",		0x54005b3b, 0xfc00ffff,	WR_1|RD_2|FP_S|FP_D,	0,		I1,		0,	0 },
 {"ceil.w.s",		"T,S",		0x54001b3b, 0xfc00ffff,	WR_1|RD_2|FP_S,		0,		I1,		0,	0 },
-{"cfc1",		"t,G",		0x5400103b, 0xfc00ffff,	WR_1|RD_C1,		0,		I1,		0,	0 },
+{"cfc1",		"t,g",		0x5400103b, 0xfc00ffff,	WR_1|RD_C1,		0,		I1,		0,	0 },
 {"cfc1",		"t,S",		0x5400103b, 0xfc00ffff,	WR_1|RD_C1,		0,		I1,		0,	0 },
-{"cfc2",		"t,G",		0x0000cd3c, 0xfc00ffff,	WR_1|RD_C2,		0,		I1,		0,	0 },
+{"cfc2",		"t,g",		0x0000cd3c, 0xfc00ffff,	WR_1|RD_C2,		0,		I1,		0,	0 },
 {"clo",			"t,s",		0x00004b3c, 0xfc00ffff,	WR_1|RD_2,		0,		I1,		0,	0 },
 {"clz",			"t,s",		0x00005b3c, 0xfc00ffff,	WR_1|RD_2,		0,		I1,		0,	0 },
 {"cop2",		"C",		0x00000002, 0xfc000007,	CP,			0,		I1,		0,	0 },
-{"ctc1",		"t,G",		0x5400183b, 0xfc00ffff,	RD_1|WR_CC,		0,		I1,		0,	0 },
+{"ctc1",		"t,g",		0x5400183b, 0xfc00ffff,	RD_1|WR_CC,		0,		I1,		0,	0 },
 {"ctc1",		"t,S",		0x5400183b, 0xfc00ffff,	RD_1|WR_CC,		0,		I1,		0,	0 },
-{"ctc2",		"t,G",		0x0000dd3c, 0xfc00ffff,	RD_1|WR_C2|WR_CC,	0,		I1,		0,	0 },
+{"ctc2",		"t,g",		0x0000dd3c, 0xfc00ffff,	RD_1|WR_C2|WR_CC,	0,		I1,		0,	0 },
 {"cvt.d.l",		"T,S",		0x5400537b, 0xfc00ffff,	WR_1|RD_2|FP_D,		0,		I1,		0,	0 },
 {"cvt.d.s",		"T,S",		0x5400137b, 0xfc00ffff,	WR_1|RD_2|FP_S|FP_D,	0,		I1,		0,	0 },
 {"cvt.d.w",		"T,S",		0x5400337b, 0xfc00ffff,	WR_1|RD_2|FP_S|FP_D,	0,		I1,		0,	0 },
Index: binutils-gdb/opcodes/mips-dis.c
===================================================================
--- binutils-gdb.orig/opcodes/mips-dis.c
+++ binutils-gdb/opcodes/mips-dis.c
@@ -1192,7 +1192,12 @@  print_reg (struct disassemble_info *info
     case OP_REG_COPRO:
       if (opcode->name[strlen (opcode->name) - 1] == '0')
 	info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]);
-      else if (opcode->name[strlen (opcode->name) - 1] == '1')
+      else
+	info->fprintf_func (info->stream, "$%d", regno);
+      break;
+
+    case OP_REG_CONTROL:
+      if (opcode->name[strlen (opcode->name) - 1] == '1')
 	info->fprintf_func (info->stream, "%s", mips_cp1_names[regno]);
       else
 	info->fprintf_func (info->stream, "$%d", regno);
Index: binutils-gdb/opcodes/mips-opc.c
===================================================================
--- binutils-gdb.orig/opcodes/mips-opc.c
+++ binutils-gdb/opcodes/mips-opc.c
@@ -195,6 +195,7 @@  decode_mips_operand (const char *p)
     case 'c': HINT (10, 16);
     case 'd': REG (5, 11, GP);
     case 'e': UINT (3, 22)
+    case 'g': REG (5, 11, CONTROL);
     case 'h': HINT (5, 11);
     case 'i': HINT (16, 0);
     case 'j': SINT (16, 0);
@@ -209,6 +210,7 @@  decode_mips_operand (const char *p)
     case 'v': OPTIONAL_REG (5, 21, GP);
     case 'w': OPTIONAL_REG (5, 16, GP);
     case 'x': REG (0, 0, GP);
+    case 'y': REG (5, 16, CONTROL);
     case 'z': MAPPED_REG (0, 0, GP, reg_0_map);
     }
   return 0;
@@ -975,13 +977,13 @@  const struct mips_opcode mips_builtin_op
 {"ceil.w.d",		"D,S",		0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D,	0,		I2,		0,	SF },
 {"ceil.w.s",		"D,S",		0x4600000e, 0xffff003f, WR_1|RD_2|FP_S,		0,		I2,		0,	EE },
 /* cfc0 is at the bottom of the table.  */
-{"cfc1",		"t,G",		0x44400000, 0xffe007ff,	WR_1|RD_C1|LC,		0,		I1,		0,	0 },
+{"cfc1",		"t,g",		0x44400000, 0xffe007ff,	WR_1|RD_C1|LC,		0,		I1,		0,	0 },
 {"cfc1",		"t,S",		0x44400000, 0xffe007ff,	WR_1|RD_C1|LC,		0,		I1,		0,	0 },
 /* cfc2 is at the bottom of the table.  */
 /* cfc3 is at the bottom of the table.  */
-{"cftc1",		"d,E",		0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC,	0,		0,		MT32,	0 },
+{"cftc1",		"d,y",		0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC,	0,		0,		MT32,	0 },
 {"cftc1",		"d,T",		0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC,	0,		0,		MT32,	0 },
-{"cftc2",		"d,E",		0x41000025, 0xffe007ff,	WR_1|RD_C2|TRAP|LC,	0,		0,		MT32,	IOCT|IOCTP|IOCT2 },
+{"cftc2",		"d,y",		0x41000025, 0xffe007ff,	WR_1|RD_C2|TRAP|LC,	0,		0,		MT32,	IOCT|IOCTP|IOCT2 },
 {"cins32",		"t,r,+p,+s",	0x70000033, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 },
 {"cins",		"t,r,+P,+S",	0x70000033, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 }, /* cins32 */
 {"cins",		"t,r,+p,+S",	0x70000032, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 },
@@ -990,13 +992,13 @@  const struct mips_opcode mips_builtin_op
 {"clz",			"d,s",		0x00000050, 0xfc1f07ff, WR_1|RD_2,		0,		I37,		0,	0 },
 {"clz",			"U,s",		0x70000020, 0xfc0007ff, WR_1|RD_2,		0,		I32|N55,	0,	I37 },
 /* ctc0 is at the bottom of the table.  */
-{"ctc1",		"t,G",		0x44c00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	0 },
+{"ctc1",		"t,g",		0x44c00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	0 },
 {"ctc1",		"t,S",		0x44c00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	0 },
 /* ctc2 is at the bottom of the table.  */
 /* ctc3 is at the bottom of the table.  */
-{"cttc1",		"t,G",		0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM,	0,		0,		MT32,	0 },
+{"cttc1",		"t,g",		0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM,	0,		0,		MT32,	0 },
 {"cttc1",		"t,S",		0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM,	0,		0,		MT32,	0 },
-{"cttc2",		"t,G",		0x41800025, 0xffe007ff,	RD_1|WR_CC|TRAP|CM,	0,		0,		MT32,	IOCT|IOCTP|IOCT2 },
+{"cttc2",		"t,g",		0x41800025, 0xffe007ff,	RD_1|WR_CC|TRAP|CM,	0,		0,		MT32,	IOCT|IOCTP|IOCT2 },
 {"cvt.d.l",		"D,S",		0x46a00021, 0xffff003f,	WR_1|RD_2|FP_D,		0,		I3_33,		0,	0 },
 {"cvt.d.s",		"D,S",		0x46000021, 0xffff003f,	WR_1|RD_2|FP_S|FP_D,	0,		I1,		0,	SF },
 {"cvt.d.w",		"D,S",		0x46800021, 0xffff003f,	WR_1|RD_2|FP_S|FP_D,	0,		I1,		0,	SF },
@@ -2106,8 +2108,8 @@  const struct mips_opcode mips_builtin_op
 /* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the
    mfhc0 and mthc0 XPA instructions, so they have been placed here
    to allow the XPA instructions to take precedence.  */
-{"ctc0",		"t,G",		0x40c00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
-{"cfc0",		"t,G",		0x40400000, 0xffe007ff,	WR_1|RD_C0|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
+{"cfc0",		"t,g",		0x40400000, 0xffe007ff,	WR_1|RD_C0|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
+{"ctc0",		"t,g",		0x40c00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
 
 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
    instructions so they are here for the latters to take precedence.  */
@@ -2121,11 +2123,11 @@  const struct mips_opcode mips_builtin_op
 {"bc2t",		"N,p",		0x49010000, 0xffe30000,	RD_CC|CBD,		0,		I32,		0,	IOCT|IOCTP|IOCT2|I37 },
 {"bc2tl",		"p",		0x49030000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2|I37 },
 {"bc2tl",		"N,p",		0x49030000, 0xffe30000,	RD_CC|CBL,		0,		I32,		0,	IOCT|IOCTP|IOCT2|I37 },
-{"cfc2",		"t,G",		0x48400000, 0xffe007ff,	WR_1|RD_C2|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
+{"cfc2",		"t,g",		0x48400000, 0xffe007ff,	WR_1|RD_C2|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
 {"cfc2",		"t,+9",		0x48400000, 0xffe007ff,	WR_1|RD_C2|LC,		0,		EE,		0,	0 },
 {"cfc2.i",		"t,+9",		0x48400001, 0xffe007ff, WR_1|RD_C2|LC,		0,		EE,		0,	0 },
 {"cfc2.ni",		"t,+9",		0x48400000, 0xffe007ff, WR_1|RD_C2|LC,		0,		EE,		0,	0 },
-{"ctc2",		"t,G",		0x48c00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
+{"ctc2",		"t,g",		0x48c00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE },
 {"ctc2",		"t,+9",		0x48c00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		EE,		0,	0 },
 {"ctc2.i",		"t,+9",		0x48c00001, 0xffe007ff, RD_1|WR_CC|CM,		0,		EE,		0,	0 },
 {"ctc2.ni",		"t,+9",		0x48c00000, 0xffe007ff, RD_1|WR_CC|CM,		0,		EE,		0,	0 },
@@ -2157,8 +2159,8 @@  const struct mips_opcode mips_builtin_op
 {"bc3fl",		"p",		0x4d020000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"bc3t",		"p",		0x4d010000, 0xffff0000,	RD_CC|CBD,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"bc3tl",		"p",		0x4d030000, 0xffff0000,	RD_CC|CBL,		0,		I2|T3,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
-{"cfc3",		"t,G",		0x4c400000, 0xffe007ff,	WR_1|RD_C3|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
-{"ctc3",		"t,G",		0x4cc00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"cfc3",		"t,g",		0x4c400000, 0xffe007ff,	WR_1|RD_C3|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
+{"ctc3",		"t,g",		0x4cc00000, 0xffe007ff,	RD_1|WR_CC|CM,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"dmfc3",		"t,G",		0x4c200000, 0xffe007ff,	WR_1|RD_C3|LC,		0,		I3,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"dmtc3",		"t,G",		0x4ca00000, 0xffe007ff,	RD_1|WR_C3|WR_CC|CM,	0,		I3,		0,	IOCT|IOCTP|IOCT2|EE|I37 },
 {"mfc3",		"t,G",		0x4c000000, 0xffe007ff,	WR_1|RD_C3|LC,		0,		I1,		0,	IOCT|IOCTP|IOCT2|EE|I37 },