[v3,2/2] sim: h8300 add special case test.

Message ID 20210526115249.70121-2-ysato@users.sourceforge.jp
State New
Headers show
Series
  • [v3,1/2] sim: h8300 Fixed different behavior in preinc/predec.
Related show

Commit Message

Yoshinori Sato May 26, 2021, 11:52 a.m.
Add test case in special destination inc/dec.

ChangeLog
2021-05-21  Yoshinori Sato  <ysato@users.sourceforge.jp>

	* addb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg>.
	* andb.s: Likewise.
	* cmpb.s: Likewise.
	* orb.s: Likewise.
	* subb.s: Likewise.
	* xorb.s: Likewise.
	* movb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg>
	          @reg+,@reg+ / @-reg,@-reg.
	@ movw.s: Likewise.
	@ movl.s: Likewise.

Changes v2.
- none.

---
 sim/testsuite/h8300/addb.s | 58 ++++++++++++++++++++++-
 sim/testsuite/h8300/andb.s | 48 +++++++++++++++++++
 sim/testsuite/h8300/cmpb.s | 44 +++++++++++++++++
 sim/testsuite/h8300/movb.s | 97 ++++++++++++++++++++++++++++++++++++--
 sim/testsuite/h8300/movl.s | 77 ++++++++++++++++++++++++++++--
 sim/testsuite/h8300/movw.s | 97 ++++++++++++++++++++++++++++++++++++--
 sim/testsuite/h8300/orb.s  | 49 ++++++++++++++++++-
 sim/testsuite/h8300/subb.s | 26 ++++++++++
 sim/testsuite/h8300/xorb.s | 27 ++++++++++-
 9 files changed, 507 insertions(+), 16 deletions(-)

-- 
2.20.1

Patch

diff --git a/sim/testsuite/h8300/addb.s b/sim/testsuite/h8300/addb.s
index f1e4ebf7264..1b96867d603 100644
--- a/sim/testsuite/h8300/addb.s
+++ b/sim/testsuite/h8300/addb.s
@@ -46,7 +46,7 @@  byte_dest:	.byte 0
 post_byte:	.byte 0
 
 	start
-	
+
 add_b_imm8_reg:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
 	;;  fixme set ccr
@@ -493,6 +493,20 @@  add_b_reg8_rdpostinc:
 	beq	.L12
 	fail
 .L12:
+	;; special case same register
+	mov.l	#byte_dest, er0
+	mov.b	@er0, r1h
+	mov.b	r0l, r1l
+	add.b	r0l, @er0+
+	inc.b	r1l
+	add.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L22
+	fail
+.L22:
+	;; restore previous value
+	mov.b	r1h, @byte_dest
 
 add_b_reg8_rdpostdec:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -527,6 +541,20 @@  add_b_reg8_rdpostdec:
 	beq	.L13
 	fail
 .L13:
+	;; special case same register
+	mov.l	#byte_dest, er0
+	mov.b	@er0, r1h
+	mov.b	r0l, r1l
+	add.b	r0l, @er0-
+	dec.b	r1l
+	add.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L23
+	fail
+.L23:
+	;; restore previous value
+	mov.b	r1h, @byte_dest
 
 add_b_reg8_rdpreinc:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -561,6 +589,20 @@  add_b_reg8_rdpreinc:
 	beq	.L14
 	fail
 .L14:
+	;; special case same register
+	mov.b	@byte_dest, r1h
+	mov.l	#pre_byte, er0
+	mov.b	r0l, r1l
+	add.b	r0l, @+er0
+	inc.b	r1l
+	add.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L24
+	fail
+.L24:
+	;; restore previous value
+	mov.b	r1h, @byte_dest
 
 add_b_reg8_rdpredec:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -595,6 +637,20 @@  add_b_reg8_rdpredec:
 	beq	.L15
 	fail
 .L15:
+	;; special case same register
+	mov.l	#post_byte, er0
+	mov.b	@byte_dest, r1h
+	mov.b	r0l, r1l
+	add.b	r0l, @-er0
+	dec.b	r1l
+	add.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L25
+	fail
+.L25:
+	;; restore previous value
+	mov.b	r1h, @byte_dest
 
 add_b_reg8_disp16:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
diff --git a/sim/testsuite/h8300/andb.s b/sim/testsuite/h8300/andb.s
index 8f11805517d..c3dc0609c15 100644
--- a/sim/testsuite/h8300/andb.s
+++ b/sim/testsuite/h8300/andb.s
@@ -126,6 +126,18 @@  and_b_imm8_rdpostinc:
 	beq	.L2
 	fail
 .L2:
+	;; special case same register
+	mov.l	#byte_dest, er0
+	mov.b	@er0, r1h
+	mov.b	r0l, r1l
+	and.b	r0l, @er0+
+	inc.b	r1l
+	and.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L22
+	fail
+.L22:
 
 and_b_imm8_rdpostdec:
 	mov	#byte_dest, er0
@@ -163,6 +175,18 @@  and_b_imm8_rdpostdec:
 	beq	.L3
 	fail
 .L3:
+	;; special case same register
+	mov.l	#byte_dest, er0
+	mov.b	@er0, r1h
+	mov.b	r0l, r1l
+	and.b	r0l, @er0-
+	dec.b	r1l
+	and.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L23
+	fail
+.L23:
 
 and_b_imm8_rdpreinc:
 	mov	#byte_dest, er0
@@ -200,6 +224,18 @@  and_b_imm8_rdpreinc:
 	beq	.L4
 	fail
 .L4:
+	;; special case same register
+	mov.l	#pre_byte, er0
+	mov.b	@byte_dest, r1h
+	mov.b	r0l, r1l
+	and.b	r0l, @+er0
+	inc.b	r1l
+	and.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L24
+	fail
+.L24:
 
 and_b_imm8_rdpredec:
 	mov	#byte_dest, er0
@@ -237,6 +273,18 @@  and_b_imm8_rdpredec:
 	beq	.L5
 	fail
 .L5:
+	;; special case same register
+	mov.l	#post_byte, er0
+	mov.b	@byte_dest, r1h
+	mov.b	r0l, r1l
+	and.b	r0l, @-er0
+	dec.b	r1l
+	and.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L25
+	fail
+.L25:
 
 .endif				; h8sx
 
diff --git a/sim/testsuite/h8300/cmpb.s b/sim/testsuite/h8300/cmpb.s
index 1a4f23c8b29..c38bf65222e 100644
--- a/sim/testsuite/h8300/cmpb.s
+++ b/sim/testsuite/h8300/cmpb.s
@@ -477,6 +477,17 @@  cmp_b_reg8_rdpostinc:
 	beq	.L9
 	fail
 .L9:
+	;; special case same register
+	mov.l	#byte_dst, er0
+	mov.b	@er0, r1h
+	mov.b	r0l, r1l
+	inc.b	r1l
+	mov.b	r1l,@er0
+	cmp.b	r0l,@er0+
+	beq	.L19
+	fail
+.L19:
+	mov.b	r1h, @byte_dst
 
 cmp_b_reg8_rdpostdec:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -530,6 +541,17 @@  cmp_b_reg8_rdpostdec:
 	beq	.L10
 	fail
 .L10:
+	;; special case same register
+	mov.l	#byte_dst, er0
+	mov.b	@er0, r1h
+	mov.b	r0l, r1l
+	dec.b	r1l
+	mov.b	r1l,@er0
+	cmp.b	r0l,@er0-
+	beq	.L20
+	fail
+.L20:
+	mov.b	r1h, @byte_dst
 
 cmp_b_reg8_rdpreinc:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -583,6 +605,17 @@  cmp_b_reg8_rdpreinc:
 	beq	.L11
 	fail
 .L11:
+	;; special case same register
+	mov.l	#pre_byte, er0
+	mov.b	@byte_dst, r1h
+	mov.b	r0l, r1l
+	inc.b	r1l
+	mov.b	r1l,@(1,er0)
+	cmp.b	r0l,@+er0
+	beq	.L21
+	fail
+.L21:
+	mov.b	r1h, @byte_dst
 
 cmp_b_reg8_rdpredec:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -636,6 +669,17 @@  cmp_b_reg8_rdpredec:
 	beq	.L12
 	fail
 .L12:
+	;; special case same register
+	mov.l	#post_byte, er0
+	mov.b	@byte_dst, r1h
+	mov.b	r0l, r1l
+	dec.b	r1l
+	mov.b	r1l,@(-1,er0)
+	cmp.b	r0l,@-er0
+	beq	.L22
+	fail
+.L22:
+	mov.b	r1h, @byte_dst
 
 cmp_b_rsind_rdind:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
diff --git a/sim/testsuite/h8300/movb.s b/sim/testsuite/h8300/movb.s
index 06d7611b8e0..6c8a686a619 100644
--- a/sim/testsuite/h8300/movb.s
+++ b/sim/testsuite/h8300/movb.s
@@ -13,6 +13,8 @@ 
 
 	.data
 	.align	4
+byte_dst_dec:
+	.byte	0
 byte_src:
 	.byte	0x77
 byte_dst:
@@ -695,6 +697,16 @@  mov_b_reg8_to_postinc:		; post-increment from register to mem
 	beq	.Lnext49
 	fail
 .Lnext49:
+	;; special case same register
+	mov.l	#byte_dst, er0
+	mov.b	r0l, r1l
+	inc.b	r1l
+	mov.b	r0l, @er0+
+	mov.b	@byte_dst, r0l
+	cmp.b	r0l, r1l
+	beq	.Lnext53
+	fail
+.Lnext53:
 	mov.b	#0, @byte_dst	; zero it again for the next use.
 
 mov_b_reg8_to_postdec:		; post-decrement from register to mem
@@ -727,6 +739,16 @@  mov_b_reg8_to_postdec:		; post-decrement from register to mem
 	beq	.Lnext50
 	fail
 .Lnext50:
+	;; special case same register
+	mov.l	#byte_dst, er0
+	mov.b	r0l, r1l
+	dec.b	r1l
+	mov.b	r0l, @er0-
+	mov.b	@byte_dst, r0l
+	cmp.b	r0l, r1l
+	beq	.Lnext54
+	fail
+.Lnext54:
 	mov.b	#0, @byte_dst	; zero it again for the next use.
 
 mov_b_reg8_to_preinc:		; pre-increment from register to mem
@@ -759,6 +781,16 @@  mov_b_reg8_to_preinc:		; pre-increment from register to mem
 	beq	.Lnext51
 	fail
 .Lnext51:
+	;; special case same register
+	mov.l	#byte_dst-1, er0
+	mov.b	r0l, r1l
+	inc.b	r1l
+	mov.b	r0l, @+er0
+	mov.b	@byte_dst, r0l
+	cmp.b	r0l, r1l
+	beq	.Lnext55
+	fail
+.Lnext55:
 	mov.b	#0, @byte_dst	; zero it again for the next use.
 .endif
 
@@ -796,6 +828,7 @@  mov_b_reg8_to_predec:		; pre-decrement from register to mem
 	;; CCR confirmation omitted
 	mov.l	#byte_dst+1, er1
 	mov.l	er1, er0
+	dec.b	r1l
 	mov.b	r0l, @-er0
 	mov.b	@byte_dst, r0l
 	cmp.b	r1l, r0l
@@ -1641,15 +1674,15 @@  mov_b_indirect_to_indirect:	; reg indirect, memory to memory
 
 	;; Now check the result of the move to memory.
 	cmp.b	@byte_src, @byte_dst
-	beq	.Lnext55
+	beq	.Lnext56
 	fail
-.Lnext55:
+.Lnext56:
 	;; Now clear the destination location, and verify that.
 	mov.b	#0, @byte_dst
 	cmp.b	@byte_src, @byte_dst
-	bne	.Lnext56
+	bne	.Lnext57
 	fail
-.Lnext56:			; OK, pass on.
+.Lnext57:			; OK, pass on.
 
 mov_b_postinc_to_postinc:	; reg post-increment, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -1691,6 +1724,20 @@  mov_b_postinc_to_postinc:	; reg post-increment, memory to memory
 	bne	.Lnext66
 	fail
 .Lnext66:			; OK, pass on.
+	;; special case same register
+	mov.l	#byte_src, er0
+	mov.b	@er0+, @er0+	; copying byte_src to byte_dst
+	test_h_gr32  byte_src+2 er0
+	cmp.b	@byte_src, @byte_dst
+	beq	.Lnext67
+	fail
+.Lnext67:
+	;; Now clear the destination location, and verify that.
+	mov.b	#0, @byte_dst
+	cmp.b	@byte_src, @byte_dst
+	bne	.Lnext68
+	fail
+.Lnext68:
 
 mov_b_postdec_to_postdec:	; reg post-decrement, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -1732,6 +1779,20 @@  mov_b_postdec_to_postdec:	; reg post-decrement, memory to memory
 	bne	.Lnext76
 	fail
 .Lnext76:			; OK, pass on.
+	;; special case same register
+	mov.l	#byte_src, er0
+	mov.b	@er0-, @er0-	; copying byte_src to byte_dst_dec
+	test_h_gr32  byte_src-2 er0
+	cmp.b	@byte_src, @byte_dst_dec
+	beq	.Lnext77
+	fail
+.Lnext77:
+	;; Now clear the destination location, and verify that.
+	mov.b	#0, @byte_dst_dec
+	cmp.b	@byte_src, @byte_dst_dec
+	bne	.Lnext78
+	fail
+.Lnext78:
 
 mov_b_preinc_to_preinc:		; reg pre-increment, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -1773,6 +1834,20 @@  mov_b_preinc_to_preinc:		; reg pre-increment, memory to memory
 	bne	.Lnext86
 	fail
 .Lnext86:				; OK, pass on.
+	;; special case same register
+	mov.l	#byte_src-1, er0
+	mov.b	@+er0, @+er0	; copying byte_src to byte_dst
+	test_h_gr32  byte_src+1 er0
+	cmp.b	@byte_src, @byte_dst
+	beq	.Lnext87
+	fail
+.Lnext87:
+	;; Now clear the destination location, and verify that.
+	mov.b	#0, @byte_dst
+	cmp.b	@byte_src, @byte_dst
+	bne	.Lnext88
+	fail
+.Lnext88:
 
 mov_b_predec_to_predec:		; reg pre-decrement, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -1814,6 +1889,20 @@  mov_b_predec_to_predec:		; reg pre-decrement, memory to memory
 	bne	.Lnext96
 	fail
 .Lnext96:			; OK, pass on.
+	;; special case same register
+	mov.l	#byte_src+1, er0
+	mov.b	@-er0, @-er0	; copying byte_src to byte_dst_dec
+	test_h_gr32  byte_src-1 er0
+	cmp.b	@byte_src, @byte_dst_dec
+	beq	.Lnext97
+	fail
+.Lnext97:
+	;; Now clear the destination location, and verify that.
+	mov.b	#0, @byte_dst_dec
+	cmp.b	@byte_src, @byte_dst_dec
+	bne	.Lnext98
+	fail
+.Lnext98:
 
 mov_b_disp2_to_disp2:		; reg 2-bit disp, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
diff --git a/sim/testsuite/h8300/movl.s b/sim/testsuite/h8300/movl.s
index 63a861345e0..8a8c16a2450 100644
--- a/sim/testsuite/h8300/movl.s
+++ b/sim/testsuite/h8300/movl.s
@@ -13,6 +13,8 @@ 
 
 	.data
 	.align	4
+long_dst_dec:
+	.long	0
 long_src:
 	.long	0x77777777
 long_dst:
@@ -1215,6 +1217,16 @@  mov_l_reg32_to_postdec:		; post-decrement from register to mem
 	beq	.Lnext50
 	fail
 .Lnext50:
+	;; special case same register
+	mov.l	#long_dst, er0
+	mov.l	er0, er1
+	subs	#4, er1
+	mov.l	er0, @er0-
+	mov.l	@long_dst, er0
+	cmp.l	er0, er1
+	beq	.Lnext54
+	fail
+.Lnext54:
 	mov.l	#0, @long_dst	; zero it again for the next use.
 
 mov_l_reg32_to_preinc:		; pre-increment from register to mem
@@ -1286,6 +1298,7 @@  mov_l_reg32_to_predec:		; pre-decrement from register to mem
 	;; CCR confirmation omitted
 	mov.l	#long_dst+4, er1
 	mov.l	er1, er0
+	subs	#4, er1
 	mov.l	er0, @-er0
 	mov.l	@long_dst, er0
 	cmp.l	er1, er0
@@ -1782,15 +1795,15 @@  mov_l_indirect_to_indirect:	; reg indirect, memory to memory
 
 	;; Now check the result of the move to memory.
 	cmp.l	@long_src, @long_dst
-	beq	.Lnext55
+	beq	.Lnext56
 	fail
-.Lnext55:
+.Lnext56:
 	;; Now clear the destination location, and verify that.
 	mov.l	#0, @long_dst
 	cmp.l	@long_src, @long_dst
-	bne	.Lnext56
+	bne	.Lnext57
 	fail
-.Lnext56:			; OK, pass on.
+.Lnext57:			; OK, pass on.
 
 mov_l_postinc_to_postinc:	; reg post-increment, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -1832,6 +1845,20 @@  mov_l_postinc_to_postinc:	; reg post-increment, memory to memory
 	bne	.Lnext66
 	fail
 .Lnext66:			; OK, pass on.
+	;; special case same register
+	mov.l	#long_src, er0
+	mov.l	@er0+, @er0+	; copying long_src to long_dst
+	test_h_gr32  long_src+8 er0
+	cmp.b	@long_src, @long_dst
+	beq	.Lnext67
+	fail
+.Lnext67:
+	;; Now clear the destination location, and verify that.
+	mov.l	#0, @long_dst
+	cmp.l	@long_src, @long_dst
+	bne	.Lnext68
+	fail
+.Lnext68:
 
 mov_l_postdec_to_postdec:	; reg post-decrement, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -1873,6 +1900,20 @@  mov_l_postdec_to_postdec:	; reg post-decrement, memory to memory
 	bne	.Lnext76
 	fail
 .Lnext76:			; OK, pass on.
+	;; special case same register
+	mov.l	#long_src, er0
+	mov.l	@er0-, @er0-	; copying long_src to long_dst_dec
+	test_h_gr32  long_src-8 er0
+	cmp.l	@long_src, @long_dst_dec
+	beq	.Lnext77
+	fail
+.Lnext77:
+	;; Now clear the destination location, and verify that.
+	mov.l	#0, @long_dst_dec
+	cmp.l	@long_src, @long_dst_dec
+	bne	.Lnext78
+	fail
+.Lnext78:
 
 mov_l_preinc_to_preinc:		; reg pre-increment, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -1914,6 +1955,20 @@  mov_l_preinc_to_preinc:		; reg pre-increment, memory to memory
 	bne	.Lnext86
 	fail
 .Lnext86:				; OK, pass on.
+	;; special case same register
+	mov.l	#long_src-4, er0
+	mov.l	@+er0, @+er0	; copying long_src to long_dst
+	test_h_gr32  long_src+4 er0
+	cmp.b	@long_src, @long_dst
+	beq	.Lnext87
+	fail
+.Lnext87:
+	;; Now clear the destination location, and verify that.
+	mov.b	#0, @long_dst
+	cmp.b	@long_src, @long_dst
+	bne	.Lnext88
+	fail
+.Lnext88:
 
 mov_l_predec_to_predec:		; reg pre-decrement, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -1955,6 +2010,20 @@  mov_l_predec_to_predec:		; reg pre-decrement, memory to memory
 	bne	.Lnext96
 	fail
 .Lnext96:			; OK, pass on.
+	;; special case same register
+	mov.l	#long_src+4, er0
+	mov.l	@-er0, @-er0	; copying long_src to long_dst_dec
+	test_h_gr32  long_src-4 er0
+	cmp.l	@long_src, @long_dst_dec
+	beq	.Lnext97
+	fail
+.Lnext97:
+	;; Now clear the destination location, and verify that.
+	mov.l	#0, @long_dst_dec
+	cmp.l	@long_src, @long_dst_dec
+	bne	.Lnext98
+	fail
+.Lnext98:
 
 mov_l_disp2_to_disp2:		; reg 2-bit disp, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
diff --git a/sim/testsuite/h8300/movw.s b/sim/testsuite/h8300/movw.s
index 2502b364d85..a13db7b3aa7 100644
--- a/sim/testsuite/h8300/movw.s
+++ b/sim/testsuite/h8300/movw.s
@@ -13,6 +13,8 @@ 
 
 	.data
 	.align	2
+word_dst_dec:
+	.word	0
 word_src:
 	.word	0x7777
 word_dst:
@@ -890,6 +892,16 @@  mov_w_reg16_to_postinc:		; post-increment from register to mem
 	beq	.Lnext49
 	fail
 .Lnext49:
+	;; special case same register
+	mov.l	#word_dst, er0
+	mov.w	r0, r1
+	inc.w	#2,r1
+	mov.w	r0, @er0+
+	mov.w	@word_dst, r0
+	cmp.w	r0, r1
+	beq	.Lnext53
+	fail
+.Lnext53:
 	mov.w	#0, @word_dst	; zero it again for the next use.
 
 mov_w_reg16_to_postdec:		; post-decrement from register to mem
@@ -922,6 +934,16 @@  mov_w_reg16_to_postdec:		; post-decrement from register to mem
 	beq	.Lnext50
 	fail
 .Lnext50:
+	;; special case same register
+	mov.l	#word_dst, er0
+	mov.w	r0, r1
+	dec.w	#2, r1
+	mov.w	r0, @er0-
+	mov.w	@word_dst, r0
+	cmp.w	r0, r1
+	beq	.Lnext54
+	fail
+.Lnext54:
 	mov.w	#0, @word_dst	; zero it again for the next use.
 
 mov_w_reg16_to_preinc:		; pre-increment from register to mem
@@ -954,6 +976,16 @@  mov_w_reg16_to_preinc:		; pre-increment from register to mem
 	beq	.Lnext51
 	fail
 .Lnext51:
+	;; special case same register
+	mov.l	#word_dst-2, er0
+	mov.w	r0, r1
+	inc.w	#2, r1
+	mov.w	r0, @+er0
+	mov.w	@word_dst, r0
+	cmp.w	r0, r1
+	beq	.Lnext55
+	fail
+.Lnext55:
 	mov.w	#0, @word_dst	; zero it again for the next use.
 .endif
 
@@ -992,6 +1024,7 @@  mov_w_reg16_to_predec:		; pre-decrement from register to mem
 	;; CCR confirmation omitted
 	mov.l	#word_dst+2, er1
 	mov.l	er1, er0
+	dec.w	#2, r1
 	mov.w	r0, @-er0
 	mov.w	@word_dst, r0
 	cmp.w	r1, r0
@@ -1479,15 +1512,15 @@  mov_w_indirect_to_indirect:	; reg indirect, memory to memory
 
 	;; Now check the result of the move to memory.
 	cmp.w	@word_src, @word_dst
-	beq	.Lnext55
+	beq	.Lnext56
 	fail
-.Lnext55:
+.Lnext56:
 	;; Now clear the destination location, and verify that.
 	mov.w	#0, @word_dst
 	cmp.w	@word_src, @word_dst
-	bne	.Lnext56
+	bne	.Lnext57
 	fail
-.Lnext56:			; OK, pass on.
+.Lnext57:			; OK, pass on.
 
 mov_w_postinc_to_postinc:	; reg post-increment, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -1529,6 +1562,20 @@  mov_w_postinc_to_postinc:	; reg post-increment, memory to memory
 	bne	.Lnext66
 	fail
 .Lnext66:			; OK, pass on.
+	;; special case same register
+	mov.l	#word_src, er0
+	mov.w	@er0+, @er0+	; copying word_src to word_dst
+	test_h_gr32  word_src+4 er0
+	cmp.w	@word_src, @word_dst
+	beq	.Lnext67
+	fail
+.Lnext67:
+	;; Now clear the destination location, and verify that.
+	mov.w	#0, @word_dst
+	cmp.b	@word_src, @word_dst
+	bne	.Lnext68
+	fail
+.Lnext68:
 
 mov_w_postdec_to_postdec:	; reg post-decrement, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -1570,6 +1617,20 @@  mov_w_postdec_to_postdec:	; reg post-decrement, memory to memory
 	bne	.Lnext76
 	fail
 .Lnext76:			; OK, pass on.
+	;; special case same register
+	mov.l	#word_src, er0
+	mov.w	@er0-, @er0-	; copying word_src to word_dst_dec
+	test_h_gr32  word_src-4 er0
+	cmp.w	@word_src, @word_dst_dec
+	beq	.Lnext77
+	fail
+.Lnext77:
+	;; Now clear the destination location, and verify that.
+	mov.w	#0, @word_dst_dec
+	cmp.w	@word_src, @word_dst_dec
+	bne	.Lnext78
+	fail
+.Lnext78:
 
 mov_w_preinc_to_preinc:		; reg pre-increment, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -1611,6 +1672,20 @@  mov_w_preinc_to_preinc:		; reg pre-increment, memory to memory
 	bne	.Lnext86
 	fail
 .Lnext86:				; OK, pass on.
+	;; special case same register
+	mov.l	#word_src-2, er0
+	mov.w	@+er0, @+er0	; copying word_src to word_dst
+	test_h_gr32  word_src+2 er0
+	cmp.w	@word_src, @word_dst
+	beq	.Lnext87
+	fail
+.Lnext87:
+	;; Now clear the destination location, and verify that.
+	mov.w	#0, @word_dst
+	cmp.w	@word_src, @word_dst
+	bne	.Lnext88
+	fail
+.Lnext88:
 
 mov_w_predec_to_predec:		; reg pre-decrement, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -1652,6 +1727,20 @@  mov_w_predec_to_predec:		; reg pre-decrement, memory to memory
 	bne	.Lnext96
 	fail
 .Lnext96:			; OK, pass on.
+	;; special case same register
+	mov.l	#word_src+2, er0
+	mov.w	@-er0, @-er0	; copying word_src to word_dst_dec
+	test_h_gr32  word_src-2 er0
+	cmp.w	@word_src, @word_dst_dec
+	beq	.Lnext97
+	fail
+.Lnext97:
+	;; Now clear the destination location, and verify that.
+	mov.w	#0, @word_dst_dec
+	cmp.w	@word_src, @word_dst_dec
+	bne	.Lnext98
+	fail
+.Lnext98:
 
 mov_w_disp2_to_disp2:		; reg 2-bit disp, memory to memory
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
diff --git a/sim/testsuite/h8300/orb.s b/sim/testsuite/h8300/orb.s
index 72da8e63a37..86ce9ed8425 100644
--- a/sim/testsuite/h8300/orb.s
+++ b/sim/testsuite/h8300/orb.s
@@ -243,7 +243,6 @@  or_b_imm8_rdpredec:
 	fail
 .L5:
 
-
 .endif
 
 or_b_reg8_reg8:
@@ -343,6 +342,18 @@  or_b_reg8_rdpostinc:
 	beq	.L7
 	fail
 .L7:
+	;; special case same register
+	mov.l	#byte_dest, er0
+	mov.b	r0l, r1l
+	mov.b	@er0, r1h
+	or.b	r0l, @er0+
+	inc.b	r1l
+	or.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L27
+	fail
+.L27:
 
 or_b_reg8_rdpostdec:
 	mov	#byte_dest, er0
@@ -381,6 +392,18 @@  or_b_reg8_rdpostdec:
 	beq	.L8
 	fail
 .L8:
+	;; special case same register
+	mov.l	#byte_dest, er0
+	mov.b	r0l, r1l
+	mov.b	@er0, r1h
+	or.b	r0l, @er0-
+	dec.b	r1l
+	or.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L28
+	fail
+.L28:
 
 or_b_reg8_rdpreinc:
 	mov	#byte_dest, er0
@@ -419,6 +442,18 @@  or_b_reg8_rdpreinc:
 	beq	.L9
 	fail
 .L9:
+	;; special case same register
+	mov.l	#pre_byte, er0
+	mov.b	r0l, r1l
+	mov.b	@byte_dest, r1h
+	or.b	r0l, @+er0
+	inc.b	r1l
+	or.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L29
+	fail
+.L29:
 
 or_b_reg8_rdpredec:
 	mov	#byte_dest, er0
@@ -457,6 +492,18 @@  or_b_reg8_rdpredec:
 	beq	.L10
 	fail
 .L10:
+	;; special case same register
+	mov.l	#post_byte, er0
+	mov.b	r0l, r1l
+	mov.b	@byte_dest, r1h
+	or.b	r0l, @-er0
+	dec.b	r1l
+	or.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L30
+	fail
+.L30:
 
 .endif
 
diff --git a/sim/testsuite/h8300/subb.s b/sim/testsuite/h8300/subb.s
index 01832948e80..628521f1d14 100644
--- a/sim/testsuite/h8300/subb.s
+++ b/sim/testsuite/h8300/subb.s
@@ -247,6 +247,20 @@  sub_b_reg8_rdpostinc:
 	beq	.L5
 	fail
 .L5:
+	;; special case same register
+	mov.l	#byte_dest, er0
+	mov.b	@er0, r1h
+	mov.b	r1h, r2l
+	mov.b	r0l, r1l
+	sub.b	r0l, @er0+
+	inc.b	r1l
+	sub.b	r1l, r1h
+	mov.b	@byte_dest, r0l
+	cmp.b	r1h, r0l
+	beq	.L25
+	fail
+.L25:
+	mov.b	r2l, @byte_dest
 
 sub_b_reg8_rdpostdec:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -281,6 +295,18 @@  sub_b_reg8_rdpostdec:
 	beq	.L6
 	fail
 .L6:
+	;; special case same register
+	mov.l	#byte_dest, er0
+	mov.b	@er0, r1h
+	mov.b	r0l, r1l
+	sub.b	r0l, @er0-
+	dec.b	r1l
+	sub.b	r1l, r1h
+	mov.b	@byte_dest, r0l
+	cmp.b	r1h, r0l
+	beq	.L26
+	fail
+.L26:
 
 .endif
 
diff --git a/sim/testsuite/h8300/xorb.s b/sim/testsuite/h8300/xorb.s
index 337c3968a47..04d43cdb9b2 100644
--- a/sim/testsuite/h8300/xorb.s
+++ b/sim/testsuite/h8300/xorb.s
@@ -155,8 +155,6 @@  xor_b_imm8_rdpostdec:
 	beq	.L3
 	fail
 .L3:
-
-
 .endif
 
 xor_b_reg8_reg8:
@@ -248,6 +246,19 @@  xor_b_reg8_rdpostinc:
 	beq	.L5
 	fail
 .L5:
+	;; special case same register
+	mov.l	#byte_dest, er0
+	mov.b	r0l, r1l
+	mov.b	@er0, r1h
+	xor.b	r0l, @er0+
+	inc.b	r1l
+	xor.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L25
+	fail
+.L25:
+	mov.b	r1h, @byte_dest
 
 xor_b_reg8_rdpostdec:
 	set_grs_a5a5		; Fill all general regs with a fixed pattern
@@ -282,6 +293,18 @@  xor_b_reg8_rdpostdec:
 	beq	.L6
 	fail
 .L6:
+	;; special case same register
+	mov.l	#byte_dest, er0
+	mov.b	r0l, r1l
+	mov.b	@er0, r1h
+	xor.b	r0l, @er0-
+	dec.b	r1l
+	xor.b	r1h, r1l
+	mov.b	@byte_dest, r0l
+	cmp.b	r1l, r0l
+	beq	.L26
+	fail
+.L26:
 
 .endif				; h8sx