[committed] RISC-V: PR27436, make operand C> work the same as >.

Message ID 1618564236-20818-1-git-send-email-nelson.chu@sifive.com
State New
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Series
  • [committed] RISC-V: PR27436, make operand C> work the same as >.
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Commit Message

Nelson Chu April 16, 2021, 9:10 a.m.
gas/
    PR 27436
    * config/tc-riscv.c (riscv_ip): make operand C> work the same as >.
    * testsuite/gas/riscv/shamt-32.d: New testcase.
    * testsuite/gas/riscv/shamt-32.l: Likewise.
    * testsuite/gas/riscv/shamt-32.s: Likewise.
    * testsuite/gas/riscv/shamt-64.d: Likewise.
    * testsuite/gas/riscv/shamt-64.l: Likewise.
    * testsuite/gas/riscv/shamt-64.s: Likewise.
---
 gas/ChangeLog                      | 11 +++++++++
 gas/config/tc-riscv.c              |  5 ++---
 gas/testsuite/gas/riscv/shamt-32.d |  3 +++
 gas/testsuite/gas/riscv/shamt-32.l | 13 +++++++++++
 gas/testsuite/gas/riscv/shamt-32.s | 31 +++++++++++++++++++++++++
 gas/testsuite/gas/riscv/shamt-64.d |  3 +++
 gas/testsuite/gas/riscv/shamt-64.l |  7 ++++++
 gas/testsuite/gas/riscv/shamt-64.s | 46 ++++++++++++++++++++++++++++++++++++++
 8 files changed, 116 insertions(+), 3 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/shamt-32.d
 create mode 100644 gas/testsuite/gas/riscv/shamt-32.l
 create mode 100644 gas/testsuite/gas/riscv/shamt-32.s
 create mode 100644 gas/testsuite/gas/riscv/shamt-64.d
 create mode 100644 gas/testsuite/gas/riscv/shamt-64.l
 create mode 100644 gas/testsuite/gas/riscv/shamt-64.s

-- 
2.7.4

Patch

diff --git a/gas/ChangeLog b/gas/ChangeLog
index ed25af6..8df1225 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,14 @@ 
+2021-04-16  Nelson Chu  <nelson.chu@sifive.com>
+
+	PR 27436
+	* config/tc-riscv.c (riscv_ip): make operand C> work the same as >.
+	* testsuite/gas/riscv/shamt-32.d: New testcase.
+	* testsuite/gas/riscv/shamt-32.l: Likewise.
+	* testsuite/gas/riscv/shamt-32.s: Likewise.
+	* testsuite/gas/riscv/shamt-64.d: Likewise.
+	* testsuite/gas/riscv/shamt-64.l: Likewise.
+	* testsuite/gas/riscv/shamt-64.s: Likewise.
+
 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 
 	* testsuite/gas/riscv/c-zero-imm.d: Compress addi a4,a4,0 to
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 2bce5e8..3fff33e 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2088,11 +2088,10 @@  riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		      || regno != 0)
 		    break;
 		  continue;
-		case '>':
+		case '>': /* Shift amount, 0 - (XLEN-1).  */
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 		      || imm_expr->X_op != O_constant
-		      || imm_expr->X_add_number <= 0
-		      || imm_expr->X_add_number >= 64)
+		      || (unsigned long) imm_expr->X_add_number >= xlen)
 		    break;
 		  ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
 		rvc_imm_done:
diff --git a/gas/testsuite/gas/riscv/shamt-32.d b/gas/testsuite/gas/riscv/shamt-32.d
new file mode 100644
index 0000000..b756109
--- /dev/null
+++ b/gas/testsuite/gas/riscv/shamt-32.d
@@ -0,0 +1,3 @@ 
+#as: -march=rv32i
+#objdump: -dr
+#error_output: shamt-32.l
diff --git a/gas/testsuite/gas/riscv/shamt-32.l b/gas/testsuite/gas/riscv/shamt-32.l
new file mode 100644
index 0000000..71feee3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/shamt-32.l
@@ -0,0 +1,13 @@ 
+.*Assembler messages:
+.*:4: Error: improper shift amount \(32\)
+.*:5: Error: improper shift amount \(63\)
+.*:9: Error: improper shift amount \(32\)
+.*:10: Error: improper shift amount \(63\)
+.*:14: Error: improper shift amount \(32\)
+.*:15: Error: improper shift amount \(63\)
+.*:20: Error: improper shift amount \(32\)
+.*:21: Error: improper shift amount \(63\)
+.*:25: Error: improper shift amount \(32\)
+.*:26: Error: improper shift amount \(63\)
+.*:30: Error: improper shift amount \(32\)
+.*:31: Error: improper shift amount \(63\)
diff --git a/gas/testsuite/gas/riscv/shamt-32.s b/gas/testsuite/gas/riscv/shamt-32.s
new file mode 100644
index 0000000..6f1a5ba
--- /dev/null
+++ b/gas/testsuite/gas/riscv/shamt-32.s
@@ -0,0 +1,31 @@ 
+	.option norvc
+	slli	a0, a0, 0
+	slli	a0, a0, 31
+	slli	a0, a0, 32
+	slli	a0, a0, 63
+
+	srli	a0, a0, 0
+	srli	a0, a0, 31
+	srli	a0, a0, 32
+	srli	a0, a0, 63
+
+	srai	a0, a0, 0
+	srai	a0, a0, 31
+	srai	a0, a0, 32
+	srai	a0, a0, 63
+
+	.option rvc
+	slli	a0, a0, 0
+	slli	a0, a0, 31
+	slli	a0, a0, 32
+	slli	a0, a0, 63
+
+	srli	a0, a0, 0
+	srli	a0, a0, 31
+	srli	a0, a0, 32
+	srli	a0, a0, 63
+
+	srai	a0, a0, 0
+	srai	a0, a0, 31
+	srai	a0, a0, 32
+	srai	a0, a0, 63
diff --git a/gas/testsuite/gas/riscv/shamt-64.d b/gas/testsuite/gas/riscv/shamt-64.d
new file mode 100644
index 0000000..563c7e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/shamt-64.d
@@ -0,0 +1,3 @@ 
+#as: -march=rv64i
+#objdump: -dr
+#error_output: shamt-64.l
diff --git a/gas/testsuite/gas/riscv/shamt-64.l b/gas/testsuite/gas/riscv/shamt-64.l
new file mode 100644
index 0000000..ded1777
--- /dev/null
+++ b/gas/testsuite/gas/riscv/shamt-64.l
@@ -0,0 +1,7 @@ 
+.*Assembler messages:
+.*:19: Error: improper shift amount \(32\)
+.*:20: Error: improper shift amount \(63\)
+.*:24: Error: improper shift amount \(32\)
+.*:25: Error: improper shift amount \(63\)
+.*:29: Error: improper shift amount \(32\)
+.*:30: Error: improper shift amount \(63\)
diff --git a/gas/testsuite/gas/riscv/shamt-64.s b/gas/testsuite/gas/riscv/shamt-64.s
new file mode 100644
index 0000000..703dfb2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/shamt-64.s
@@ -0,0 +1,46 @@ 
+	.option norvc
+	slli	a0, a0, 0
+	slli	a0, a0, 31
+	slli	a0, a0, 32
+	slli	a0, a0, 63
+
+	srli	a0, a0, 0
+	srli	a0, a0, 31
+	srli	a0, a0, 32
+	srli	a0, a0, 63
+
+	srai	a0, a0, 0
+	srai	a0, a0, 31
+	srai	a0, a0, 32
+	srai	a0, a0, 63
+
+	slliw	a0, a0, 0
+	slliw	a0, a0, 31
+	slliw	a0, a0, 32
+	slliw	a0, a0, 63
+
+	srliw	a0, a0, 0
+	srliw	a0, a0, 31
+	srliw	a0, a0, 32
+	srliw	a0, a0, 63
+
+	sraiw	a0, a0, 0
+	sraiw	a0, a0, 31
+	sraiw	a0, a0, 32
+	sraiw	a0, a0, 63
+
+	.option rvc
+	slli	a0, a0, 0
+	slli	a0, a0, 31
+	slli	a0, a0, 32
+	slli	a0, a0, 63
+
+	srli	a0, a0, 0
+	srli	a0, a0, 31
+	srli	a0, a0, 32
+	srli	a0, a0, 63
+
+	srai	a0, a0, 0
+	srai	a0, a0, 31
+	srai	a0, a0, 32
+	srai	a0, a0, 63