[integration,0/4] RISC-V/rvv: Update rvv from v01.0 to v1.0 except zve feature.

Message ID 20210621062703.8369-1-nelson.chu@sifive.com
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  • RISC-V/rvv: Update rvv from v01.0 to v1.0 except zve feature.
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Nelson Chu June 21, 2021, 6:26 a.m.
Hi Guys,

The series of patches update the rvv from version v0.10 to v1.0-rc1,
except the zve features.  Since zve[32|64][xfd] namings cannot be parsed
by current architecture string parser, and may conflict to the ISA spec,
https://github.com/riscv/riscv-v-spec/issues/697.

There are four patches as follows,
RISC-V/rvv: Added assembly pseudoinstructions, vfabs.v.
RISC-V/rvv: Changed assembler mnemonic for mask loads/stores.
RISC-V/rvv: Changed assembler mnemonic for unordered floating-point reductions.
RISC-V/rvv: Removed Zvamo from standard v, and then changed version to 1.0.

I plan to create the binutils-integration-2.37 branch when the 2.37 release
is ready.  But I'm not sure if the zve naming issue can be resolved before
the date, so probably keep the rvv v0.10 in the binutils-integration-2.37
is more safe, and the rvv v1.0-rc1 features can continue to be updated on
binutils-integration-branch.

Thanks
Nelson