Show patches with: Submitter = Jim Wilson       |    State = Action Required       |    Archived = No       |   57 patches
Patch Series S/W/F Date Submitter Delegate State
[24/24] RISC-V sim: Fix divw and remw. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[23/24] RISC-V sim: Add zicsr support. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[22/24] RISC-V sim: Support compressed FP instructions. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[21/24] RISC-V sim: Fix mingw builds. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[20/24] RISC-V sim: Set brk to _end if possible. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[19/24] RISC-V sim: Improve tracing for slt* instructions. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[18/24] RISC-V sim: Improve branch tracing. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[17/24] RISC-V sim: Fix tracing typo. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[16/24] RISC-V sim: Check sbrk argument. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[15/24] RISC-V sim: Improve cycle and instret counts. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[14/24] RISC-V sim: Add csrr*i instructions. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[13/24] RISC-V sim: Add gettimeofday. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[12/24] RISC-V sim: Add compressed support. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[11/24] RISC-V sim: Fix ebreak, part 2. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[10/24] RISC-V sim: Fix ebreak. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[09/24] RISC-V sim: Fix syscall fallback. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[08/24] RISC-V sim: Add brk syscall. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[07/24] RISC-V sim: Add link syscall support. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[06/24] RISC-V: Add fp support. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[05/24] RISC-V sim: Fix stack pointer alignment. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[04/24] RISC-V sim: More atomic fixes. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[03/24] RISC-V sim: Atomic fixes. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[02/24] RISC-V sim: Fix for jalr. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
[01/24] RISC-V sim: Fix fence.i. RISC-V sim: Update from riscv-gnu-toolchain. 0 0 0 2021-04-17 Jim Wilson New
Aarch64 sim fix for gcc-10 miscompilation. Aarch64 sim fix for gcc-10 miscompilation. 0 0 0 2021-04-08 Jim Wilson New
[2/2] Improve comments in print-utils.h. fix ARI warnings for RISC-V port and fallout 0 0 0 2019-10-10 Jim Wilson New
[1/2] RISC-V: Fix two ARI warnings. fix ARI warnings for RISC-V port and fallout 0 0 0 2019-10-10 Jim Wilson New
RISC-V: Allow setting breakpoints at invalid addresses. RISC-V: Allow setting breakpoints at invalid addresses. 0 0 0 2019-04-13 Jim Wilson New
RISC-V: Add FP register core file support. RISC-V: Add FP register core file support. 0 0 0 2019-02-06 Jim Wilson New
RISC-V: Fix wrong use of s0 register name. RISC-V: Fix wrong use of s0 register name. 0 0 0 2019-01-01 Jim Wilson New
RISC-V: Correct printing of MSTATUS and MISA. RISC-V: Correct printing of MSTATUS and MISA. 0 0 0 2018-12-13 Jim Wilson New
[3/3,v2] RISC-V: Fix unnamed arg alignment in registers. RISC-V: gdb.base/gnu_vector fixes. 0 0 0 2018-11-13 Jim Wilson New
[2/3,v2] RISC-V: Handle vector type alignment. RISC-V: gdb.base/gnu_vector fixes. 0 0 0 2018-11-13 Jim Wilson New
[1/3,v2] RISC-V: Give stack slots same align as XLEN. RISC-V: gdb.base/gnu_vector fixes. 0 0 0 2018-11-13 Jim Wilson New
[3/3] RISC-V: gdb.base/gnu_vector fixes. RISC-V: gdb.base/gnu_vector fixes. 0 0 0 2018-11-06 Jim Wilson New
[2/3] RISC-V: gdb.base/gnu_vector fixes. RISC-V: gdb.base/gnu_vector fixes. 0 0 0 2018-11-06 Jim Wilson New
[1/3] RISC-V: gdb.base/gnu_vector fixes. RISC-V: gdb.base/gnu_vector fixes. 0 0 0 2018-11-06 Jim Wilson New
RISC-V: Fix xlen to flen typo in FP reg handling. RISC-V: Fix xlen to flen typo in FP reg handling. 0 0 0 2018-11-03 Jim Wilson New
RISC-V: Don't allow unaligned breakpoints. RISC-V: Don't allow unaligned breakpoints. 0 0 0 2018-11-01 Jim Wilson New
RISC-V: Force variables to .data for code_elim. RISC-V: Force variables to .data for code_elim. 0 0 0 2018-10-26 Jim Wilson New
[2/2] RISC-V: Linux signal frame support. RISC-V: Linux signal frame support. 0 0 0 2018-10-26 Jim Wilson New
[1/2] RISC-V: Linux signal frame support. RISC-V: Linux signal frame support. 0 0 0 2018-10-25 Jim Wilson New
[2/2] RISC-V: NaN-box FP values smaller than an FP register. RISC-V: Improve FP register support. 0 0 0 2018-10-19 Jim Wilson New
[1/2] RISC-V: Print FP regs as union of float types. RISC-V: Improve FP register support. 0 0 0 2018-10-19 Jim Wilson New
Fix riscv-linux native gdb build failure. Fix riscv-linux native gdb build failure. 0 0 0 2018-08-28 Jim Wilson New
[5/5] RISC-V: Add configure support for riscv*-linux*. Untitled series #6275 0 0 0 2018-08-09 Jim Wilson New
[4/5] RISC-V: Add native linux support. Untitled series #6274 0 0 0 2018-08-08 Jim Wilson New
[3/5] RISC-V: Add linux target support. Untitled series #6269 0 0 0 2018-08-08 Jim Wilson New
[5/5] RISC-V: Add configure support riscv*-linux*. RISC-V Linux native port 0 0 0 2018-08-08 Jim Wilson Superseded
[4/5] RISC-V: Add native linux support. RISC-V Linux native port 0 0 0 2018-08-08 Jim Wilson Superseded
[3/5] RISC-V: Add linux target support. RISC-V Linux native port 0 0 0 2018-08-08 Jim Wilson Superseded
[2/5] RISC-V: Add software single step support. RISC-V Linux native port 0 0 0 2018-08-08 Jim Wilson New
[1/5] RISC-V: Make riscv_isa_xlen a global function. RISC-V Linux native port 0 0 0 2018-08-08 Jim Wilson New
RISC-V: Don't decrement pc after break. RISC-V: Don't decrement pc after break. 0 0 0 2018-07-17 Jim Wilson New
RISC-V: Add osabi support. RISC-V: Add osabi support. 0 0 0 2018-07-04 Jim Wilson New
RISC-V: Add software single step support. RISC-V: Add software single step support. 0 0 0 2018-07-04 Jim Wilson Superseded
RISC-V: Correct legacy misa register number. RISC-V: Correct legacy misa register number. 0 0 0 2018-07-04 Jim Wilson New