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: Submitter =
Nelson Chu
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| 101 patches
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Patch
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Submitter
Delegate
State
[committed,v2] RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.
[committed,v2] RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.
0 0 0
2021-02-18
Nelson Chu
New
[committed] RISC-V: PR27200, allow the first input non-ABI binary to be linked with any one.
[committed] RISC-V: PR27200, allow the first input non-ABI binary to be linked with any one.
0 0 0
2021-02-17
Nelson Chu
New
[committed,2/2] RISC-V: PR27348, Remove the obsolete OP_*CUSTOM_IMM.
[committed,1/2] RISC-V: PR27348, Remove obsolete Xcustom support.
0 0 0
2021-02-05
Nelson Chu
New
[committed,1/2] RISC-V: PR27348, Remove obsolete Xcustom support.
[committed,1/2] RISC-V: PR27348, Remove obsolete Xcustom support.
0 0 0
2021-02-05
Nelson Chu
New
[committed] RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.
[committed] RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.
0 0 0
2021-02-04
Nelson Chu
New
RISC-V: Add bfd/cpu-riscv.h to support all spec versions controling.
RISC-V: Add bfd/cpu-riscv.h to support all spec versions controling.
0 0 0
2021-01-28
Nelson Chu
Superseded
RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.
RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.
0 0 0
2021-01-27
Nelson Chu
New
RISCV/ld: allow the first input non-ABI binary to be linked with any one.
RISCV/ld: allow the first input non-ABI binary to be linked with any one.
0 0 0
2021-01-22
Nelson Chu
New
RISC-V: Fixed the indent that caused by the previous commits accidentally.
RISC-V: Fixed the indent that caused by the previous commits accidentally.
0 0 0
2021-01-15
Nelson Chu
New
[3/3] RISC-V: Indent and GNU coding standards tidy, also aligned the code.
[1/3] RISC-V: Comments tidy and improvement.
0 0 0
2021-01-15
Nelson Chu
New
[2/3] RISC-V: Error and warning messages tidy.
[1/3] RISC-V: Comments tidy and improvement.
0 0 0
2021-01-15
Nelson Chu
New
[1/3] RISC-V: Comments tidy and improvement.
[1/3] RISC-V: Comments tidy and improvement.
0 0 0
2021-01-15
Nelson Chu
New
ld: Just xfail riscv little endian targets for compressed1d.d test.
ld: Just xfail riscv little endian targets for compressed1d.d test.
0 0 0
2021-01-08
Nelson Chu
New
[v3] RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).
[v3] RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).
0 0 0
2021-01-07
Nelson Chu
New
ld: xfail riscv64be-*-* for ld-scripts/empty-address-2 tests.
ld: xfail riscv64be-*-* for ld-scripts/empty-address-2 tests.
0 0 0
2021-01-06
Nelson Chu
New
[v2] RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).
[v2] RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).
0 0 0
2021-01-05
Nelson Chu
New
RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).
RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).
0 0 0
2021-01-05
Nelson Chu
Superseded
RISC-V: Fix the merged orders of Z* extension for linker.
RISC-V: Fix the merged orders of Z* extension for linker.
0 0 0
2021-01-04
Nelson Chu
New
RISC-V: Improve multiple relax passes problem.
RISC-V: Improve multiple relax passes problem.
0 0 0
2020-12-18
Nelson Chu
New
RISC-V: Ouput __global_pointer$ as dynamic symbol when generating dynamic PDE.
RISC-V: Ouput __global_pointer$ as dynamic symbol when generating dynamic PDE.
0 0 0
2020-12-16
Nelson Chu
New
[3/3] RISC-V: Add -menable-experimental-extensions option.
RISC-V: Add -menable-experimental-extensions and support bitmanip instructions
0 0 0
2020-12-15
Nelson Chu
New
[2/3] RISC-V: Define pseudo rev/orc/zip/unzip as alias instructions.
RISC-V: Add -menable-experimental-extensions and support bitmanip instructions
0 0 0
2020-12-15
Nelson Chu
New
[1/3] RISC-V: Support riscv bitmanip instructions.
RISC-V: Add -menable-experimental-extensions and support bitmanip instructions
0 0 0
2020-12-15
Nelson Chu
New
[v2] RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.
[v2] RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.
0 0 0
2020-12-09
Nelson Chu
New
RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.
RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.
0 0 0
2020-12-09
Nelson Chu
Superseded
RISC-V: Dump CSR according to the elf privileged spec attributes.
RISC-V: Dump CSR according to the elf privileged spec attributes.
0 0 0
2020-12-08
Nelson Chu
New
[v2] RISC-V: Control fence.i and csr instructions by zifencei and zicsr.
[v2] RISC-V: Control fence.i and csr instructions by zifencei and zicsr.
0 0 0
2020-12-08
Nelson Chu
New
RISC-V: Control fence.i and csr instructions by zifencei and zicsr.
RISC-V: Control fence.i and csr instructions by zifencei and zicsr.
0 0 0
2020-12-03
Nelson Chu
Superseded
RISC-V: Add DT_RISCV_GP dynamic tag to fix the uninitialized gp for ifunc.
RISC-V: Add DT_RISCV_GP dynamic tag to fix the uninitialized gp for ifunc.
0 0 0
2020-12-01
Nelson Chu
New
[8/8] RISC-V: Fix the order checking for Z* extension.
RISC-V: Architecture string improvement
0 0 0
2020-11-27
Nelson Chu
New
[7/8] RISC-V: Support to add implicit extensions for G.
RISC-V: Architecture string improvement
0 0 0
2020-11-27
Nelson Chu
New
[6/8] RISC-V: Support to add implicit extensions.
RISC-V: Architecture string improvement
0 0 0
2020-11-27
Nelson Chu
New
[5/8] RISC-V: Improve the version parsing for arch string.
RISC-V: Architecture string improvement
0 0 0
2020-11-27
Nelson Chu
New
[4/8] RISC-V: Remove the unimplemented extensions.
RISC-V: Architecture string improvement
0 0 0
2020-11-27
Nelson Chu
New
[3/8] RISC-V: Add zifencei and prefixed h class extensions.
RISC-V: Architecture string improvement
0 0 0
2020-11-27
Nelson Chu
New
[2/8] RISC-V: Don't allow any uppercase letter in the arch string.
RISC-V: Architecture string improvement
0 0 0
2020-11-27
Nelson Chu
New
[1/8] RISC-V: Minor cleanup and testcases improvement for arch string parser.
RISC-V: Architecture string improvement
0 0 0
2020-11-27
Nelson Chu
New
RISC-V: Relax PCREL to GPREL while doing other relaxations is dangerous.
RISC-V: Relax PCREL to GPREL while doing other relaxations is dangerous.
0 0 0
2020-11-18
Nelson Chu
New
[v2] RISC-V: Update ABI to the elf_flags after parsing elf attributes.
[v2] RISC-V: Update ABI to the elf_flags after parsing elf attributes.
0 0 0
2020-11-05
Nelson Chu
New
RISC-V: Update ABI to the elf_flags after parsing elf attributes.
RISC-V: Update ABI to the elf_flags after parsing elf attributes.
0 0 0
2020-10-20
Nelson Chu
New
[v3,2/2] RISC-V: Fix that IRELATIVE relocs may be inserted to the wrong place.
RISC-V: Support GNU indirect functions
0 0 0
2020-10-07
Nelson Chu
New
[v3,1/2] RISC-V: Support GNU indirect functions.
RISC-V: Support GNU indirect functions
0 0 0
2020-10-07
Nelson Chu
New
RISC-V: Treat R_RISCV_CALL and R_RISCV_CALL_PLT as the same in check_relocs.
RISC-V: Treat R_RISCV_CALL and R_RISCV_CALL_PLT as the same in check_relocs.
0 0 0
2020-08-26
Nelson Chu
New
[3/3] RISC-V: Minor cleanup and typos when merging priv spec attributes.
Allow to link objects with different versions of ISA, and fix some minor issues
0 0 0
2020-08-20
Nelson Chu
New
[2/3] RISC-V: Report warnings rather than errors for the mis-matched ISA versions.
Allow to link objects with different versions of ISA, and fix some minor issues
0 0 0
2020-08-20
Nelson Chu
New
[1/3] RISC-V: Improve the error message for the mis-matched ISA versions.
Allow to link objects with different versions of ISA, and fix some minor issues
0 0 0
2020-08-20
Nelson Chu
New
[v2,8/8] RISC-V: Change bfd_link_executable back to !bfd_link_pic in check_relocs.
[v2,1/8] RISC-V: Support GNU indirect functions.
0 0 0
2020-08-07
Nelson Chu
New
[v2,7/8] RISC-V: Consider the different module testcases for IFUNC.
[v2,1/8] RISC-V: Support GNU indirect functions.
0 0 0
2020-08-07
Nelson Chu
New
[v2,6/8] RISC-V: Rewrite the IFUNC testcases.
[v2,1/8] RISC-V: Support GNU indirect functions.
0 0 0
2020-08-07
Nelson Chu
New
[v2,5/8] RISC-V: Remove the IFUNC testcases since their name are hard to understand.
[v2,1/8] RISC-V: Support GNU indirect functions.
0 0 0
2020-08-07
Nelson Chu
New
[v2,4/8] RISC-V: Use NEED_IFUNC_SECTIONS to check if we need IFUNC sections or not.
[v2,1/8] RISC-V: Support GNU indirect functions.
0 0 0
2020-08-07
Nelson Chu
New
[v2,3/8] RISC-V: Resolve the TEXTREL warning and redundant R_RISCV_NONE for IFUNC.
[v2,1/8] RISC-V: Support GNU indirect functions.
0 0 0
2020-08-07
Nelson Chu
New
[v2,2/8] RISC-V: Treat R_RISCV_CALL and R_RISCV_CALL_PLT as the same.
[v2,1/8] RISC-V: Support GNU indirect functions.
0 0 0
2020-08-07
Nelson Chu
Superseded
[v2,1/8] RISC-V: Support GNU indirect functions.
[v2,1/8] RISC-V: Support GNU indirect functions.
0 0 0
2020-08-07
Nelson Chu
New
[v2,0/8] RISC-V: Support GNU indirect functions
0 0 0
2020-08-07
Nelson Chu
New
RISC-V: Support GNU indirect functions.
RISC-V: Support GNU indirect functions.
0 0 0
2020-07-08
Nelson Chu
Superseded
RISC-V: Support GNU indirect functions.
RISC-V: Support GNU indirect functions.
0 0 0
2020-07-08
Nelson Chu
Superseded
[v2,3/3] RISC-V: Support new CSR macro DECLARE_CSR_REUSE to handle the reused CSR.
[v2,1/3] RISC-V: Cleanup the include/opcode/riscv-opc.h.
0 0 0
2020-06-25
Nelson Chu
New
[v2,2/3] RISC-V: Support debug and float CSR as the unprivileged ones.
[v2,1/3] RISC-V: Cleanup the include/opcode/riscv-opc.h.
0 0 0
2020-06-25
Nelson Chu
New
[v2,1/3] RISC-V: Cleanup the include/opcode/riscv-opc.h.
[v2,1/3] RISC-V: Cleanup the include/opcode/riscv-opc.h.
0 0 0
2020-06-25
Nelson Chu
New
[v2,0/3] Support unprivileged CSR and new DECLARE_CSR_REUSE macro
0 0 0
2020-06-25
Nelson Chu
New
[v2] RISC-V: Generate ELF priv attributes if priv instruction are explicited used.
[v2] RISC-V: Generate ELF priv attributes if priv instruction are explicited used.
0 0 0
2020-06-22
Nelson Chu
New
[2/2] RISC-V: Report warning when linking the objects with different priv specs.
RISC-V: Update linker behavior when merging the elf priv spec attributes
0 0 0
2020-06-17
Nelson Chu
New
[1/2] RISC-V: Don't assume the priv attributes are in order when handling them.
RISC-V: Update linker behavior when merging the elf priv spec attributes
0 0 0
2020-06-17
Nelson Chu
New
RISC-V: Generate ELF priv attributes if priv instruction are explicited used.
RISC-V: Generate ELF priv attributes if priv instruction are explicited used.
0 0 0
2020-06-17
Nelson Chu
New
RISC-V: Drop the privileged spec v1.9 support.
RISC-V: Drop the privileged spec v1.9 support.
0 0 0
2020-06-11
Nelson Chu
New
RISC-V: Support debug and float CSR as the unprivileged ones.
RISC-V: Support debug and float CSR as the unprivileged ones.
0 0 0
2020-06-08
Nelson Chu
New
RISC-V: Fix the error when building RISC-V linux native gdbserver.
RISC-V: Fix the error when building RISC-V linux native gdbserver.
0 0 0
2020-06-02
Nelson Chu
New
[2/2] RISC-V: The object without priv spec attributes can be linked with any object.
RISC-V: Fix the conflicting priv spec problems
0 0 0
2020-05-30
Nelson Chu
New
[1/2] RISC-V: Don't generate the ELF privilege attributes when no CSR are used.
RISC-V: Fix the conflicting priv spec problems
0 0 0
2020-05-30
Nelson Chu
New
RISC-V: Add elfNN_riscv_mkobject to initialize RISC-V tdata.
RISC-V: Add elfNN_riscv_mkobject to initialize RISC-V tdata.
0 0 0
2020-05-13
Nelson Chu
New
[v2,7/9] RISC-V: Make privilege spec attributes workable.
Untitled series #25193
0 0 0
2020-05-06
Nelson Chu
New
[v2,4/9] RISC-V: Support configure options to set ISA versions by default.
Untitled series #25193
0 0 0
2020-05-06
Nelson Chu
New
[5/7] RISC-V: Make privilege spec attributes work.
Untitled series #24618
0 0 0
2020-04-18
Nelson Chu
New
[v2,2/2] RISC-V: Support assembler modifier %got_pcrel_hi.
Add description for the RISC-V relocatable modifiers in as doc
0 0 0
2020-03-04
Nelson Chu
New
[v2,1/2] RISC-V: Add description for RISC-V Modifiers to as doc.
Add description for the RISC-V relocatable modifiers in as doc
0 0 0
2020-03-04
Nelson Chu
New
[2/2] RISC-V: Support assembler modifier %got_pcrel_hi.
Add description for the RISC-V relocatable modifiers in as doc
0 0 0
2020-03-03
Nelson Chu
Superseded
[1/2] RISC-V: Add description for RISC-V Modifiers to as doc.
Add description for the RISC-V relocatable modifiers in as doc
0 0 0
2020-03-03
Nelson Chu
New
RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.
RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.
0 0 0
2020-02-19
Nelson Chu
New
[3/3] RISC-V: Support the read-only CSR checking.
RISC-V: Support more rigorous check for CSR
0 0 0
2020-02-12
Nelson Chu
New
[2/3] RISC-V: Disable the CSR checking by default.
RISC-V: Support more rigorous check for CSR
0 0 0
2020-02-12
Nelson Chu
New
[1/3] RISC-V: Support the ISA-dependent CSR checking.
RISC-V: Support more rigorous check for CSR
0 0 0
2020-02-12
Nelson Chu
New
RISC-V: Add description for -march-attr/-mno-arch-attr options in gas doc.
RISC-V: Add description for -march-attr/-mno-arch-attr options in gas doc.
0 0 0
2020-02-06
Nelson Chu
New
[v4,3/3] RISC-V: Support the read-only CSR checking.
RISC-V: Support more rigorous check for CSR
0 0 0
2020-02-05
Nelson Chu
Superseded
[v4,2/3] RISC-V: Disable the CSR checking by default.
RISC-V: Support more rigorous check for CSR
0 0 0
2020-02-05
Nelson Chu
Superseded
[v4,1/3] RISC-V: Support the ISA-dependent CSR checking.
RISC-V: Support more rigorous check for CSR
0 0 0
2020-02-05
Nelson Chu
Superseded
[v3,4/4] RISC-V: Disable the CSR checking by default.
RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.
0 0 0
2019-12-16
Nelson Chu
New
[v3,3/4] RISC-V: Support the read-only CSR checking.
RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.
0 0 0
2019-12-16
Nelson Chu
New
[v3,2/4] RISC-V: Support the ISA-dependent CSR checking.
RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.
0 0 0
2019-12-16
Nelson Chu
New
[v3,1/4] RISC-V: Update the CSR to privilege spec 1.12.
RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.
0 0 0
2019-12-16
Nelson Chu
New
[v2,4/4] RISC-V: Disable the CSR checking by default.
[v2,1/4] RISC-V: Update the CSR to privilege spec 1.12.
0 0 0
2019-12-03
Nelson Chu
Superseded
[v2,3/4] RISC-V: Support the read-only CSR checking.
[v2,1/4] RISC-V: Update the CSR to privilege spec 1.12.
0 0 0
2019-12-03
Nelson Chu
Superseded
[v2,2/4] RISC-V: Support the ISA-dependent CSR checking.
[v2,1/4] RISC-V: Update the CSR to privilege spec 1.12.
0 0 0
2019-12-03
Nelson Chu
Superseded
[v2,1/4] RISC-V: Update the CSR to privilege spec 1.12.
[v2,1/4] RISC-V: Update the CSR to privilege spec 1.12.
0 0 0
2019-12-03
Nelson Chu
Superseded
[4/4] RISC-V: Disable the CSR checking by default.
RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.
0 0 0
2019-11-25
Nelson Chu
Superseded
[3/4] RISC-V: Support the read-only CSR checking.
RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.
0 0 0
2019-11-25
Nelson Chu
Superseded
[2/4] RISC-V: Support the ISA-dependent CSR checking.
RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.
0 0 0
2019-11-25
Nelson Chu
Superseded
[1/4] RISC-V: Update the CSR to privilege spec 1.12.
RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.
0 0 0
2019-11-25
Nelson Chu
Superseded
[4/4] RISC-V: Disable the CSR checking by default.
Untitled series #19800
0 0 0
2019-11-25
Nelson Chu
Superseded
[3/4] RISC-V: Support the read-only CSR checking.
Untitled series #19800
0 0 0
2019-11-25
Nelson Chu
Superseded
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