[Integration,6/6] RISC-V/zfh: Support .float16 directive for assembler.

Message ID 1617097017-16776-7-git-send-email-nelson.chu@sifive.com
State Superseded
Headers show
Series
  • RISC-V: The prototype of the integration and working branches for binutils.
Related show

Commit Message

Nelson Chu March 30, 2021, 9:36 a.m.
This probably need to be sent to mainline rather than here.

gas/
    * config/tc-riscv.c (FLT_CHARS): Added h and H.
    (riscv_pseudo_table): Added .float16.
    * read.c (hex_float): Handle case 'h' and 'H'.
    * testsuite/gas/riscv/extended/extended.exp: Updated.
    * testsuite/gas/riscv/extended/float16.d: New testcase.
    * testsuite/gas/riscv/extended/float16.s: Likewise.
---
 gas/config/tc-riscv.c                         |  3 ++-
 gas/read.c                                    |  5 +++++
 gas/testsuite/gas/riscv/extended/extended.exp |  1 +
 gas/testsuite/gas/riscv/extended/float16.d    | 10 ++++++++++
 gas/testsuite/gas/riscv/extended/float16.s    | 21 +++++++++++++++++++++
 5 files changed, 39 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/riscv/extended/float16.d
 create mode 100644 gas/testsuite/gas/riscv/extended/float16.s

-- 
2.7.4

Comments

Jim Wilson March 30, 2021, 11:14 p.m. | #1
On Tue, Mar 30, 2021 at 2:37 AM Nelson Chu <nelson.chu@sifive.com> wrote:

> This probably need to be sent to mainline rather than here.

>


The riscv parts should go on a branch.  The read.c part of the patch could
perhaps be offered for master, but without a target using it, it won't be
useful there.  So putting it on a branch makes sense for now.

Jim

Patch

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 71b60f1..7c49932 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -586,7 +586,7 @@  const char EXP_CHARS[] = "eE";
 
 /* Chars that mean this number is a floating point constant.
    As in 0f12.456 or 0d1.2345e12.  */
-const char FLT_CHARS[] = "rRsSfFdDxXpP";
+const char FLT_CHARS[] = "rRsSfFdDxXpPhH";
 
 /* Indicate we are already assemble any instructions or not.  */
 static bfd_boolean start_assemble = FALSE;
@@ -4577,6 +4577,7 @@  static const pseudo_typeS riscv_pseudo_table[] =
   {"sleb128", s_riscv_leb128, 1},
   {"insn", s_riscv_insn, 0},
   {"attribute", s_riscv_attribute, 0},
+  {"float16", float_cons, 'h'},
 
   { NULL, NULL, 0 },
 };
diff --git a/gas/read.c b/gas/read.c
index 3e76065..812bb87 100644
--- a/gas/read.c
+++ b/gas/read.c
@@ -4830,6 +4830,11 @@  hex_float (int float_type, char *bytes)
 
   switch (float_type)
     {
+    case 'h':
+    case 'H':
+      length = 2;
+      break;
+
     case 'f':
     case 'F':
     case 's':
diff --git a/gas/testsuite/gas/riscv/extended/extended.exp b/gas/testsuite/gas/riscv/extended/extended.exp
index c9111cb..e200797 100644
--- a/gas/testsuite/gas/riscv/extended/extended.exp
+++ b/gas/testsuite/gas/riscv/extended/extended.exp
@@ -32,6 +32,7 @@  if [istarget riscv*-*-*] {
     run_dump_tests "vector-insns-fail-permutation"
     run_dump_tests "vector-insns-fail-zvamo"
     run_dump_tests "fp-zfh-insns"
+    run_dump_tests "float16"
 
     run_dump_tests "sifive-insns"
 
diff --git a/gas/testsuite/gas/riscv/extended/float16.d b/gas/testsuite/gas/riscv/extended/float16.d
new file mode 100644
index 0000000..e75971d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/float16.d
@@ -0,0 +1,10 @@ 
+# source: float16.s
+# objdump: -sj .data
+# as:
+
+.*:[ 	]+file format .*
+
+Contents of section \.data:
+ 0000 004adf2f 191cff7b 0100ff03 0004003c.*
+ 0010 013cff7f 007c00fc 00000080 00bce7bb.*
+ 0020 fffb0042 004a3e60 007e017e.*
diff --git a/gas/testsuite/gas/riscv/extended/float16.s b/gas/testsuite/gas/riscv/extended/float16.s
new file mode 100644
index 0000000..709ea0a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/float16.s
@@ -0,0 +1,21 @@ 
+.data
+	.float16 12.0
+	.float16 0.123
+	.float16 0.004
+	.float16 65504
+	.float16 5.9605e-8
+	.float16 6.0976e-5
+	.float16 6.1035e-5
+	.float16 1
+	.float16 1.001
+	.float16 NaN
+	.float16 +Inf
+	.float16 -Inf
+	.float16 +0
+	.float16 -0
+	.float16 -1
+	.float16 -0.98765
+	.float16 -65504
+	.float16 3.0, 12.0, 543.123
+	.float16 0h:7e00	# qNaNh
+	.float16 0h:7e01	# sNaNh