[PATCHv3,7/9] gdb/riscv: make riscv target description names global

Message ID f699fdee89e030af1ebe109aa5996916b40b4acb.1613410057.git.andrew.burgess@embecosm.com
State New
Headers show
Series
  • Bare-metal core dumps for RISC-V
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Commit Message

Andrew Burgess Feb. 15, 2021, 5:29 p.m.
A later commit will need the names of the RISC-V target description
features in files other than riscv-tdep.c.  This commit just makes the
names global strings that can be accessed from other riscv-*.c files.

There should be no user visible changes after this commit.

gdb/ChangeLog:

        * riscv-tdep.c (riscv_feature_name_csr): Define.
        (riscv_feature_name_cpu): Define.
        (riscv_feature_name_fpu): Define.
        (riscv_feature_name_virtual): Define.
        (riscv_xreg_feature): Use riscv_feature_name_cpu.
        (riscv_freg_feature): Use riscv_feature_name_fpu.
        (riscv_virtual_feature): Use riscv_feature_name_virtual.
        (riscv_csr_feature): Use riscv_feature_name_csr.
        * riscv-tdep.h (riscv_feature_name_csr): Declare.
---
 gdb/ChangeLog    | 12 ++++++++++++
 gdb/riscv-tdep.c | 14 ++++++++++----
 gdb/riscv-tdep.h |  3 +++
 3 files changed, 25 insertions(+), 4 deletions(-)

-- 
2.25.4

Patch

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 460746a9bfe..ee56d840c36 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -94,6 +94,12 @@  static unsigned int riscv_debug_unwinder = 0;
 
 static unsigned int riscv_debug_gdbarch = 0;
 
+/* The names of the RISC-V target description features.  */
+const char *riscv_feature_name_csr = "org.gnu.gdb.riscv.csr";
+static const char *riscv_feature_name_cpu = "org.gnu.gdb.riscv.cpu";
+static const char *riscv_feature_name_fpu = "org.gnu.gdb.riscv.fpu";
+static const char *riscv_feature_name_virtual = "org.gnu.gdb.riscv.virtual";
+
 /* Cached information about a frame.  */
 
 struct riscv_unwind_cache
@@ -257,7 +263,7 @@  riscv_register_feature::register_info::check
 struct riscv_xreg_feature : public riscv_register_feature
 {
   riscv_xreg_feature ()
-    : riscv_register_feature ("org.gnu.gdb.riscv.cpu")
+    : riscv_register_feature (riscv_feature_name_cpu)
   {
     m_registers =  {
       { RISCV_ZERO_REGNUM + 0, { "zero", "x0" } },
@@ -354,7 +360,7 @@  static const struct riscv_xreg_feature riscv_xreg_feature;
 struct riscv_freg_feature : public riscv_register_feature
 {
   riscv_freg_feature ()
-    : riscv_register_feature ("org.gnu.gdb.riscv.fpu")
+    : riscv_register_feature (riscv_feature_name_fpu)
   {
     m_registers =  {
       { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" } },
@@ -482,7 +488,7 @@  static const struct riscv_freg_feature riscv_freg_feature;
 struct riscv_virtual_feature : public riscv_register_feature
 {
   riscv_virtual_feature ()
-    : riscv_register_feature ("org.gnu.gdb.riscv.virtual")
+    : riscv_register_feature (riscv_feature_name_virtual)
   {
     m_registers =  {
       { RISCV_PRIV_REGNUM, { "priv" } }
@@ -518,7 +524,7 @@  static const struct riscv_virtual_feature riscv_virtual_feature;
 struct riscv_csr_feature : public riscv_register_feature
 {
   riscv_csr_feature ()
-    : riscv_register_feature ("org.gnu.gdb.riscv.csr")
+    : riscv_register_feature (riscv_feature_name_csr)
   {
     m_registers = {
 #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER)		\
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index d1f1cf17ba8..154097df5d0 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -160,4 +160,7 @@  extern void riscv_supply_regset (const struct regset *regset,
 				  struct regcache *regcache, int regnum,
 				  const void *regs, size_t len);
 
+/* The names of the RISC-V target description features.  */
+extern const char *riscv_feature_name_csr;
+
 #endif /* RISCV_TDEP_H */