[26/29] rs6000: Add Power9 builtins

Message ID 2a03b57d52eafb4d37cbd1e1e4bc9558a2545d5d.1595809584.git.wschmidt@linux.ibm.com
State New
Headers show
Series
  • rs6000: Auto-generate builtins from descriptions [V2]
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Commit Message

Bill Schmidt July 27, 2020, 2:14 p.m.
From: Bill Schmidt <wschmidt@linux.ibm.com>


2020-07-26  Bill Schmidt  <wschmidt@linux.ibm.com>

	* config/rs6000/rs6000-builtin-new.def: Add power9,
	power9-vector, and power9-64 builtins.
---
 gcc/config/rs6000/rs6000-builtin-new.def | 354 +++++++++++++++++++++++
 1 file changed, 354 insertions(+)

-- 
2.17.1

Comments

xionghu luo via Gcc-patches July 30, 2020, 5:15 p.m. | #1
On Mon, 2020-07-27 at 09:14 -0500, Bill Schmidt wrote:
> From: Bill Schmidt <wschmidt@linux.ibm.com>

> 

> 2020-07-26  Bill Schmidt  <wschmidt@linux.ibm.com>

> 

> 	* config/rs6000/rs6000-builtin-new.def: Add power9,

> 	power9-vector, and power9-64 builtins.

> ---

>  gcc/config/rs6000/rs6000-builtin-new.def | 354

> +++++++++++++++++++++++

>  1 file changed, 354 insertions(+)

> 

> diff --git a/gcc/config/rs6000/rs6000-builtin-new.def

> b/gcc/config/rs6000/rs6000-builtin-new.def

> index 2f918c1d69e..1338f543a6a 100644

> --- a/gcc/config/rs6000/rs6000-builtin-new.def

> +++ b/gcc/config/rs6000/rs6000-builtin-new.def

> @@ -2394,3 +2394,357 @@

>      XSCVSPDPN vsx_xscvspdpn {}

> 

> 

> +; Power9 vector builtins.

> +[power9-vector]

> +  const vus __builtin_altivec_convert_4f32_8i16 (vf, vf);

> +    CONVERT_4F32_8I16 convert_4f32_8i16 {}

> +

> +  const unsigned int __builtin_altivec_first_match_index_v16qi (vsc,

> vsc);

> +    VFIRSTMATCHINDEX_V16QI first_match_index_v16qi {}


Noting a "vus" on the previous entry, was/is a define for "ui ==
unsigned int" considered?
Similar question for subsequent types that are still fully spelled out.
(unsigned char, unsigned short, ... )


<snip>

> +; Miscellaneour P9 functions



Miscellaneous   :-) 

<snip>

> +

> +

> +; These things need some review to see whether they really require

> +; MASK_POWERPC64.  For xsxexpdp, this seems to be fine for 32-bit,

> +; because the result will always fit in 32 bits and the return

> +; value is SImode; but the pattern currently requires TARGET_64BIT.

> +; On the other hand, xsssigdp has a result that doesn't fit in


perhaps xsxsigdp ? 


> +; 32 bits, and the return value is DImode, so it seems that

> +; TARGET_64BIT (actually TARGET_POWERPC64) is justified.  TBD. ####

> +[power9-64]

> +; The following two are inexplicably named __builtin_altivec_* while

> +; their load counterparts are __builtin_vsx_*.  Need to deprecate

> +; these interfaces in favor of the other naming scheme (or vice

> versa).


Thanks
-Will
xionghu luo via Gcc-patches July 30, 2020, 5:44 p.m. | #2
On 7/30/20 12:15 PM, will schmidt wrote:
> On Mon, 2020-07-27 at 09:14 -0500, Bill Schmidt wrote:

>> From: Bill Schmidt <wschmidt@linux.ibm.com>

>>

>> 2020-07-26  Bill Schmidt  <wschmidt@linux.ibm.com>

>>

>> 	* config/rs6000/rs6000-builtin-new.def: Add power9,

>> 	power9-vector, and power9-64 builtins.

>> ---

>>   gcc/config/rs6000/rs6000-builtin-new.def | 354

>> +++++++++++++++++++++++

>>   1 file changed, 354 insertions(+)

>>

>> diff --git a/gcc/config/rs6000/rs6000-builtin-new.def

>> b/gcc/config/rs6000/rs6000-builtin-new.def

>> index 2f918c1d69e..1338f543a6a 100644

>> --- a/gcc/config/rs6000/rs6000-builtin-new.def

>> +++ b/gcc/config/rs6000/rs6000-builtin-new.def

>> @@ -2394,3 +2394,357 @@

>>       XSCVSPDPN vsx_xscvspdpn {}

>>

>>

>> +; Power9 vector builtins.

>> +[power9-vector]

>> +  const vus __builtin_altivec_convert_4f32_8i16 (vf, vf);

>> +    CONVERT_4F32_8I16 convert_4f32_8i16 {}

>> +

>> +  const unsigned int __builtin_altivec_first_match_index_v16qi (vsc,

>> vsc);

>> +    VFIRSTMATCHINDEX_V16QI first_match_index_v16qi {}

> Noting a "vus" on the previous entry, was/is a define for "ui ==

> unsigned int" considered?

> Similar question for subsequent types that are still fully spelled out.

> (unsigned char, unsigned short, ... )


I did consider it, but I feel there's a balance between keeping the 
lines short and keeping them readable.  The vector types are egregious 
space hogs, so I felt I needed to abbreviate them to avoid line wrap, 
but in most cases the scalar variables are fine with normal types.  One 
of those YMMV situations.
>

>

> <snip>

>

>> +; Miscellaneour P9 functions

>

> Miscellaneous   :-)


Thanks :)
>

> <snip>

>

>> +

>> +

>> +; These things need some review to see whether they really require

>> +; MASK_POWERPC64.  For xsxexpdp, this seems to be fine for 32-bit,

>> +; because the result will always fit in 32 bits and the return

>> +; value is SImode; but the pattern currently requires TARGET_64BIT.

>> +; On the other hand, xsssigdp has a result that doesn't fit in

> perhaps xsxsigdp ?


Indeed!

Thanks very much for the review!

Bill

>

>

>> +; 32 bits, and the return value is DImode, so it seems that

>> +; TARGET_64BIT (actually TARGET_POWERPC64) is justified.  TBD. ####

>> +[power9-64]

>> +; The following two are inexplicably named __builtin_altivec_* while

>> +; their load counterparts are __builtin_vsx_*.  Need to deprecate

>> +; these interfaces in favor of the other naming scheme (or vice

>> versa).

> Thanks

> -Will

>

>

Patch

diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 2f918c1d69e..1338f543a6a 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -2394,3 +2394,357 @@ 
     XSCVSPDPN vsx_xscvspdpn {}
 
 
+; Power9 vector builtins.
+[power9-vector]
+  const vus __builtin_altivec_convert_4f32_8i16 (vf, vf);
+    CONVERT_4F32_8I16 convert_4f32_8i16 {}
+
+  const unsigned int __builtin_altivec_first_match_index_v16qi (vsc, vsc);
+    VFIRSTMATCHINDEX_V16QI first_match_index_v16qi {}
+
+  const unsigned int __builtin_altivec_first_match_index_v8hi (vss, vss);
+    VFIRSTMATCHINDEX_V8HI first_match_index_v8hi {}
+
+  const unsigned int __builtin_altivec_first_match_index_v4si (vsi, vsi);
+    VFIRSTMATCHINDEX_V4SI first_match_index_v4si {}
+
+  const unsigned int __builtin_altivec_first_match_or_eos_index_v16qi (vsc, vsc);
+    VFIRSTMATCHOREOSINDEX_V16QI first_match_or_eos_index_v16qi {}
+
+  const unsigned int __builtin_altivec_first_match_or_eos_index_v8hi (vss, vss);
+    VFIRSTMATCHOREOSINDEX_V8HI first_match_or_eos_index_v8hi {}
+
+  const unsigned int __builtin_altivec_first_match_or_eos_index_v4si (vsi, vsi);
+    VFIRSTMATCHOREOSINDEX_V4SI first_match_or_eos_index_v4si {}
+
+  const unsigned int __builtin_altivec_first_mismatch_index_v16qi (vsc, vsc);
+    VFIRSTMISMATCHINDEX_V16QI first_mismatch_index_v16qi {}
+
+  const unsigned int __builtin_altivec_first_mismatch_index_v8hi (vss, vss);
+    VFIRSTMISMATCHINDEX_V8HI first_mismatch_index_v8hi {}
+
+  const unsigned int __builtin_altivec_first_mismatch_index_v4si (vsi, vsi);
+    VFIRSTMISMATCHINDEX_V4SI first_mismatch_index_v4si {}
+
+  const unsigned int __builtin_altivec_first_mismatch_or_eos_index_v16qi (vsc, vsc);
+    VFIRSTMISMATCHOREOSINDEX_V16QI first_mismatch_or_eos_index_v16qi {}
+
+  const unsigned int __builtin_altivec_first_mismatch_or_eos_index_v8hi (vss, vss);
+    VFIRSTMISMATCHOREOSINDEX_V8HI first_mismatch_or_eos_index_v8hi {}
+
+  const unsigned int __builtin_altivec_first_mismatch_or_eos_index_v4si (vsi, vsi);
+    VFIRSTMISMATCHOREOSINDEX_V4SI first_mismatch_or_eos_index_v4si {}
+
+  const vuc __builtin_altivec_vadub (vuc, vuc);
+    VADUB vaduv16qi3 {}
+
+  const vus __builtin_altivec_vaduh (vus, vus);
+    VADUH vaduv8hi3 {}
+
+  const vui __builtin_altivec_vaduw (vui, vui);
+    VADUW vaduv4si3 {}
+
+  const vull __builtin_altivec_vbpermd (vull, vuc);
+    VBPERMD altivec_vbpermd {}
+
+  const signed int __builtin_altivec_vclzlsbb_v16qi (vsc);
+    VCLZLSBB_V16QI vclzlsbb_v16qi {}
+
+  const signed int __builtin_altivec_vclzlsbb_v4si (vsi);
+    VCLZLSBB_V4SI vclzlsbb_v4si {}
+
+  const signed int __builtin_altivec_vclzlsbb_v8hi (vss);
+    VCLZLSBB_V8HI vclzlsbb_v8hi {}
+
+  const vsc __builtin_altivec_vctzb (vsc);
+    VCTZB ctzv16qi2 {}
+
+  const vsll __builtin_altivec_vctzd (vsll);
+    VCTZD ctzv2di2 {}
+
+  const vss __builtin_altivec_vctzh (vss);
+    VCTZH ctzv8hi2 {}
+
+  const vsi __builtin_altivec_vctzw (vsi);
+    VCTZW ctzv4si2 {}
+
+  const signed int __builtin_altivec_vctzlsbb_v16qi (vsc);
+    VCTZLSBB_V16QI vctzlsbb_v16qi {}
+
+  const signed int __builtin_altivec_vctzlsbb_v4si (vsi);
+    VCTZLSBB_V4SI vctzlsbb_v4si {}
+
+  const signed int __builtin_altivec_vctzlsbb_v8hi (vss);
+    VCTZLSBB_V8HI vctzlsbb_v8hi {}
+
+  const signed int __builtin_altivec_vcmpaeb_p (vsc, vsc);
+    VCMPAEB_P vector_ae_v16qi_p {pred}
+
+  const signed int __builtin_altivec_vcmpaed_p (vsll, vsll);
+    VCMPAED_P vector_ae_v2di_p {pred}
+
+  const signed int __builtin_altivec_vcmpaedp_p (vd, vd);
+    VCMPAEDP_P vector_ae_v2df_p {pred}
+
+  const signed int __builtin_altivec_vcmpaefp_p (vf, vf);
+    VCMPAEFP_P vector_ae_v4sf_p {pred}
+
+  const signed int __builtin_altivec_vcmpaeh_p (vss, vss);
+    VCMPAEH_P vector_ae_v8hi_p {pred}
+
+  const signed int __builtin_altivec_vcmpaew_p (vsi, vsi);
+    VCMPAEW_P vector_ae_v4si_p {pred}
+
+  const vbc __builtin_altivec_vcmpneb (vsc, vsc);
+    CMPNEB vcmpneb {}
+
+  const signed int __builtin_altivec_vcmpneb_p (vsc, vsc);
+    VCMPNEB_P vector_ne_v16qi_p {pred}
+
+  const signed int __builtin_altivec_vcmpned_p (vsll, vsll);
+    VCMPNED_P vector_ne_v2di_p {pred}
+
+  const signed int __builtin_altivec_vcmpnedp_p (vd, vd);
+    VCMPNEDP_P vector_ne_v2df_p {pred}
+
+  const signed int __builtin_altivec_vcmpnefp_p (vf, vf);
+    VCMPNEFP_P vector_ne_v4sf_p {pred}
+
+  const vbs __builtin_altivec_vcmpneh (vss, vss);
+    CMPNEH vcmpneh {}
+
+  const signed int __builtin_altivec_vcmpneh_p (vss, vss);
+    VCMPNEH_P vector_ne_v8hi_p {pred}
+
+  const vbi __builtin_altivec_vcmpnew (vsi, vsi);
+    CMPNEW vcmpnew {}
+
+  const signed int __builtin_altivec_vcmpnew_p (vsi, vsi);
+    VCMPNEW_P vector_ne_v4si_p {pred}
+
+  const vbc __builtin_altivec_vcmpnezb (vsc, vsc);
+    CMPNEZB vcmpnezb {}
+
+  const signed int __builtin_altivec_vcmpnezb_p (signed int, vsc, vsc);
+    VCMPNEZB_P vector_nez_v16qi_p {pred}
+
+  const vbs __builtin_altivec_vcmpnezh (vss, vss);
+    CMPNEZH vcmpnezh {}
+
+  const signed int __builtin_altivec_vcmpnezh_p (signed int, vss, vss);
+    VCMPNEZH_P vector_nez_v8hi_p {pred}
+
+  const vbi __builtin_altivec_vcmpnezw (vsi, vsi);
+    CMPNEZW vcmpnezw {}
+
+  const signed int __builtin_altivec_vcmpnezw_p (vsi, vsi);
+    VCMPNEZW_P vector_nez_v4si_p {pred}
+
+  const unsigned char __builtin_altivec_vextublx (unsigned int, vuc);
+    VEXTUBLX vextublx {}
+
+  const unsigned char __builtin_altivec_vextubrx (unsigned int, vuc);
+    VEXTUBRX vextubrx {}
+
+  const unsigned short __builtin_altivec_vextuhlx (unsigned int, vus);
+    VEXTUHLX vextuhlx {}
+
+  const unsigned short __builtin_altivec_vextuhrx (unsigned int, vus);
+    VEXTUHRX vextuhrx {}
+
+  const unsigned int __builtin_altivec_vextuwlx (unsigned int, vui);
+    VEXTUWLX vextuwlx {}
+
+  const unsigned int __builtin_altivec_vextuwrx (unsigned int, vui);
+    VEXTUWRX vextuwrx {}
+
+  const vsll __builtin_altivec_vprtybd (vsll);
+    VPRTYBD parityv2di2 {}
+
+  const vsq __builtin_altivec_vprtybq (vsq);
+    VPRTYBQ parityv1ti2 {}
+
+  const vsi __builtin_altivec_vprtybw (vsi);
+    VPRTYBW parityv4si2 {}
+
+  const vull __builtiin_altivec_vrldmi (vull, vull, vull);
+    VRLDMI altivec_vrldmi {}
+
+  const vull __builtin_altivec_vrldnm (vull, vull);
+    VRLDNM altivec_vrldnm {}
+
+  const vui __builtin_altivec_vrlwmi (vui, vui, vui);
+    VRLWMI altivec_vrlwmi {}
+
+  const vui __builtin_altivec_vrlwnm (vui, vui);
+    VRLWNM altivec_vrlwnm {}
+
+  const vuc __builtin_altivec_vslv (vuc, vuc);
+    VSLV vslv {}
+
+  const vuc __builtin_altivec_vsrv (vuc, vuc);
+    VSRV vsrv {}
+
+  const signed int __builtin_scalar_byte_in_range (unsigned char, unsigned int);
+    CMPRB cmprb {}
+
+  const signed int __builtin_scalar_byte_in_either_range (unsigned char, unsigned int);
+    CMPRB2 cmprb2 {}
+
+  const vull __builtin_vsx_extract4b (vuc, signed int);
+    EXTRACT4B extract4b {}
+
+  const vull __builtin_vsx_extract_exp_dp (vd);
+    VEEDP xvxexpdp {}
+
+  const vui __builtin_vsx_extract_exp_sp (vf);
+    VEESP xvxexpsp {}
+
+  const vull __builtin_vsx_extract_sig_dp (vd);
+    VESDP xvxsigdp {}
+
+  const vui __builtin_vsx_extract_sig_sp (vf);
+    VESSP xvxsigsp {}
+
+  const vuc __builtin_vsx_insert4b (vsi, vuc, const int[0,12]);
+    INSERT4B insert4b {}
+
+  const vd __builtin_vsx_insert_exp_dp (vop, vull);
+    VIEDP xviexpdp {}
+
+  const vf __builtin_vsx_insert_exp_sp (vop, vull);
+    VIESP xviexpsp {}
+
+  const signed int __builtin_vsx_scalar_cmp_exp_dp_eq (double, double);
+    VSCEDPEQ xscmpexpdp_eq {}
+
+  const signed int __builtin_vsx_scalar_cmp_exp_dp_gt (double, double);
+    VSCEDPGT xscmpexpdp_gt {}
+
+  const signed int __builtin_vsx_scalar_cmp_exp_dp_lt (double, double);
+    VSCEDPLT xscmpexpdp_lt {}
+
+  const signed int __builtin_vsx_scalar_cmp_exp_dp_unordered (double, double);
+    VSCEDPUO xscmpexpdp_unordered {}
+
+  const unsigned int __builtin_vsx_scalar_test_data_class_dp (double, signed int);
+    VSTDCDP xststdcdp {}
+
+  const unsigned int __builtin_vsx_scalar_test_data_class_sp (float, signed int);
+    VSTDCSP xststdcsp {}
+
+  const unsigned int __builtin_vsx_scalar_test_neg_dp (double);
+    VSTDCNDP xststdcnegdp {}
+
+  const unsigned int __builtin_vsx_scalar_test_neg_sp (float);
+    VSTDCNSP xststdcnegsp {}
+
+  const unsigned long long __builtin_vsx_test_data_class_dp (vd, signed int);
+    VTDCDP xvtstdcdp {}
+
+  const unsigned int __builtin_vsx_test_data_class_sp (vf, signed int);
+    VTDCSP xvtstdcsp {}
+
+  const vf __builtin_vsx_vextract_fp_from_shorth (vus);
+    VEXTRACT_FP_FROM_SHORTH vextract_fp_from_shorth {}
+
+  const vf __builtin_vsx_vextract_fp_from_shortl (vus);
+    VEXTRACT_FP_FROM_SHORTL vextract_fp_from_shortl {}
+
+  const vd __builtin_vsx_xxbrd_v2df (vd);
+    XXBRD_V2DF p9_xxbrd_v2df {}
+
+  const vsll __builtin_vsx_xxbrd_v2di (vsll);
+    XXBRD_V2DI p9_xxbrd_v2di {}
+
+  const vss __builtin_vsx_xxbrh_v8hi (vss);
+    XXBRH_V8HI p9_xxbrh_v8hi {}
+
+  const vsc __builtin_vsx_xxbrq_v16qi (vsc);
+    XXBRQ_V16QI p9_xxbrq_v16qi {}
+
+  const vsq __builtin_vsx_xxbrq_v1ti (vsq);
+    XXBRQ_V1TI p9_xxbrq_v1ti {}
+
+  const vf __builtin_vsx_xxbrw_v4sf (vf);
+    XXBRW_V4SF p9_xxbrw_v4sf {}
+
+  const vsi __builtin_vsx_xxbrw_v4si (vsi);
+    XXBRW_V4SI p9_xxbrw_v4si {}
+
+
+; Miscellaneour P9 functions
+[power9]
+  signed long long __builtin_darn ();
+    DARN darn {}
+
+  signed int __builtin_darn_32 ();
+    DARN_32 darn_32 {}
+
+  signed long long __builtin_darn_raw ();
+    DARN_RAW darn_raw {}
+
+  const signed int __builtin_dtstsfi_eq_dd (unsigned int, _Decimal64);
+    TSTSFI_EQ_DD dfptstsfi_eq_dd {}
+
+  const signed int __builtin_dtstsfi_eq_td (unsigned int, _Decimal128);
+    TSTSFI_EQ_TD dfptstsfi_eq_td {}
+
+  const signed int __builtin_dtstsfi_gt_dd (unsigned int, _Decimal64);
+    TSTSFI_GT_DD dfptstsfi_gt_dd {}
+
+  const signed int __builtin_dtstsfi_gt_td (unsigned int, _Decimal128);
+    TSTSFI_GT_TD dfptstsfi_gt_td {}
+
+  const signed int __builtin_dtstsfi_lt_dd (unsigned int, _Decimal64);
+    TSTSFI_LT_DD dfptstsfi_lt_dd {}
+
+  const signed int __builtin_dtstsfi_lt_td (unsigned int, _Decimal128);
+    TSTSFI_LT_TD dfptstsfi_lt_td {}
+
+  const signed int __builtin_dtstsfi_ov_dd (unsigned int, _Decimal64);
+    TSTSFI_OV_DD dfptstsfi_unordered_dd {}
+
+  const signed int __builtin_dtstsfi_ov_td (unsigned int, _Decimal128);
+    TSTSFI_OV_TD dfptstsfi_unordered_td {}
+
+
+; These things need some review to see whether they really require
+; MASK_POWERPC64.  For xsxexpdp, this seems to be fine for 32-bit,
+; because the result will always fit in 32 bits and the return
+; value is SImode; but the pattern currently requires TARGET_64BIT.
+; On the other hand, xsssigdp has a result that doesn't fit in
+; 32 bits, and the return value is DImode, so it seems that
+; TARGET_64BIT (actually TARGET_POWERPC64) is justified.  TBD. ####
+[power9-64]
+; The following two are inexplicably named __builtin_altivec_* while
+; their load counterparts are __builtin_vsx_*.  Need to deprecate
+; these interfaces in favor of the other naming scheme (or vice versa).
+  void __builtin_altivec_xst_len_r (vop, void *, unsigned long long);
+    XST_LEN_R xst_len_r {}
+
+  void __builtin_altivec_stxvl (vop, void *, unsigned long long);
+    STXVL stxvl {}
+
+  const signed int __builtin_scalar_byte_in_set (unsigned char, unsigned long long);
+    CMPEQB cmpeqb {}
+
+  pure vop __builtin_vsx_lxvl (void *, unsigned long long);
+    LXVL lxvl {}
+
+  const unsigned int __builtin_vsx_scalar_extract_exp (double);
+    VSEEDP xsxexpdp {}
+
+  const unsigned long long __builtin_vsx_scalar_extract_sig (double);
+    VSESDP xsxsigdp {}
+
+  const double __builtin_vsx_scalar_insert_exp (unsigned long long, unsigned long long);
+    VSIEDP xsiexpdp {}
+
+  const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned long long);
+    VSIEDPF xsiexpdpf {}
+
+  pure vuc __builtin_vsx_xl_len_r (void *, unsigned long long);
+    XL_LEN_R xl_len_r {}
+
+