[24/29] rs6000: Add Power7 builtins

Message ID 87bf0201bda42d9a6ca863762f456c2fab13d800.1595809584.git.wschmidt@linux.ibm.com
State New
Headers show
Series
  • rs6000: Auto-generate builtins from descriptions [V2]
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Commit Message

Bill Schmidt July 27, 2020, 2:14 p.m.
From: Bill Schmidt <wschmidt@linux.ibm.com>


2020-07-26  Bill Schmidt  <wschmidt@linux.ibm.com>

	* config/rs6000/rs6000-builtin-new.def: Add power7 and
	power7-64 builtins.
---
 gcc/config/rs6000/rs6000-builtin-new.def | 39 ++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

-- 
2.17.1

Patch

diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 1cb019bd4fb..0a17cad446c 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1938,3 +1938,42 @@ 
     XXSPLTD_V2DI vsx_xxspltd_v2di {}
 
 
+; Power7 builtins (ISA 2.06).
+[power7]
+  const unsigned int __builtin_addg6s (unsigned int, unsigned int);
+    ADDG6S addg6s {}
+
+  const signed long long __builtin_bpermd (signed long long, signed long long);
+    BPERMD bpermd_di {}
+
+  const unsigned int __builtin_cbcdtd (unsigned int);
+    CBCDTD cbcdtd {}
+
+  const unsigned int __builtin_cdtbcd (unsigned int);
+    CDTBCD cdtbcd {}
+
+  const signed int __builtin_divwe (signed int, signed int);
+    DIVWE dive_si {}
+
+  const unsigned int __builtin_divweu (unsigned int, unsigned int);
+    DIVWEU diveu_si {}
+
+  const vsq __builtin_pack_vector_int128 (unsigned long long, unsigned long long);
+    PACK_V1TI packv1ti {}
+
+  void __builtin_ppc_speculation_barrier ();
+    SPECBARR speculation_barrier {}
+
+  const unsigned long long __builtin_unpack_vector_int128 (vsq, const int<1>);
+    UNPACK_V1TI unpackv1ti {}
+
+
+; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing).
+[power7-64]
+  const signed long long __builtin_divde (signed long long, signed long long);
+    DIVDE dive_di {}
+
+  const unsigned long long __builtin_divdeu (unsigned long long, unsigned long long);
+    DIVDEU diveu_di {}
+
+