x86: Add SwapSources

Message ID 20200702150504.250296-1-hjl.tools@gmail.com
State New
Headers show
Series
  • x86: Add SwapSources
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Commit Message

David Faust via Binutils July 2, 2020, 3:05 p.m.
We check register-only source operand to decide if two source operands of
VEX encoded instructions should be swapped.  But source operands in AMX
instructions with two source operands swapped are all register-only
operand.  Add SwapSources to indicate 2 two source operands should be
swapped.

gas/

	* config/tc-i386.c (build_modrm_byte): Check vexswapsources to
	swap two source operands.

opcodes/

	* i386-gen.c (opcode_modifiers): Add VexSwapSources.
	* i386-opc.h (VexSwapSources): New.
	(i386_opcode_modifier): Add vexswapsources.
	* i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
	with two source operands.
	* i386-tbl.h: Regenerated.
---
 gas/config/tc-i386.c |    6 +-
 opcodes/i386-gen.c   |    1 +
 opcodes/i386-opc.h   |    4 +
 opcodes/i386-opc.tbl |   10 +-
 opcodes/i386-tbl.h   | 7964 +++++++++++++++++++++---------------------
 5 files changed, 3994 insertions(+), 3991 deletions(-)

Comments

Jan Beulich July 2, 2020, 3:21 p.m. | #1
On 02.07.2020 17:05, H.J. Lu via Binutils wrote:
> We check register-only source operand to decide if two source operands of

> VEX encoded instructions should be swapped.  But source operands in AMX

> instructions with two source operands swapped are all register-only

> operand.  Add SwapSources to indicate 2 two source operands should be

> swapped.


I take it this is what then will avoid the new VEXOP3?

Jan
David Faust via Binutils July 2, 2020, 3:38 p.m. | #2
On Thu, Jul 2, 2020 at 8:21 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> On 02.07.2020 17:05, H.J. Lu via Binutils wrote:

> > We check register-only source operand to decide if two source operands of

> > VEX encoded instructions should be swapped.  But source operands in AMX

> > instructions with two source operands swapped are all register-only

> > operand.  Add SwapSources to indicate 2 two source operands should be

> > swapped.

>

> I take it this is what then will avoid the new VEXOP3?

>


Yes.

-- 
H.J.

Patch

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 46823e24fc..2e0eb24753 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -7884,10 +7884,8 @@  build_modrm_byte (void)
 	      i386_operand_type op;
 	      unsigned int vvvv;
 
-	      /* Check register-only source operand when two source
-		 operands are swapped.  */
-	      if (!i.tm.operand_types[source].bitfield.baseindex
-		  && i.tm.operand_types[dest].bitfield.baseindex)
+	      /* Swap two source operands if needed.  */
+	      if (i.tm.opcode_modifier.swapsources)
 		{
 		  vvvv = source;
 		  source = dest;
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index e7454db5d4..7230f87344 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -676,6 +676,7 @@  static bitfield opcode_modifiers[] =
   BITFIELD (Disp8MemShift),
   BITFIELD (NoDefMask),
   BITFIELD (ImplicitQuadGroup),
+  BITFIELD (SwapSources),
   BITFIELD (Optimize),
   BITFIELD (ATTMnemonic),
   BITFIELD (ATTSyntax),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 174438698e..c65febbe81 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -635,6 +635,9 @@  enum
    */
   ImplicitQuadGroup,
 
+  /* Two source operands are swapped.  */
+  SwapSources,
+
   /* Support encoding optimization.  */
   Optimize,
 
@@ -710,6 +713,7 @@  typedef struct i386_opcode_modifier
   unsigned int disp8memshift:3;
   unsigned int nodefmask:1;
   unsigned int implicitquadgroup:1;
+  unsigned int swapsources:1;
   unsigned int optimize:1;
   unsigned int attmnemonic:1;
   unsigned int attsyntax:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index ded96884c0..cd6833c5ae 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2320,14 +2320,14 @@  xend, 0, 0xf01d5, None, 3, CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld
 xtest, 0, 0xf01d6, None, 3, CpuHLE|CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 
 // BMI2 instructions.
-bzhi, 3, 0xf5, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
+bzhi, 3, 0xf5, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
 mulx, 3, 0xf2f6, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
 pdep, 3, 0xf2f5, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
 pext, 3, 0xf3f5, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
 rorx, 3, 0xf2f0, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=2|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
-sarx, 3, 0xf3f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
-shlx, 3, 0x66f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
-shrx, 3, 0xf2f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
+sarx, 3, 0xf3f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
+shlx, 3, 0x66f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
+shrx, 3, 0xf2f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
 
 // FMA4 instructions
 
@@ -2437,7 +2437,7 @@  lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|IgnoreSize|No_bSuf|No_wSuf|No
 // BMI instructions
 
 andn, 3, 0xf2, None, 1, CpuBMI, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
-bextr, 3, 0xf7, None, 1, CpuBMI, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
+bextr, 3, 0xf7, None, 1, CpuBMI, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
 blsi, 2, 0xf3, 0x3, 1, CpuBMI, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
 blsmsk, 2, 0xf3, 0x2, 1, CpuBMI, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
 blsr, 2, 0xf3, 0x1, 1, CpuBMI, Modrm|CheckRegSize|Vex128|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }