[COMMITTED,MSP430,SIM] Fix simulation of RRUX instruction

Message ID 20200122215700.36914a84@jozef-kubuntu
State New
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  • [COMMITTED,MSP430,SIM] Fix simulation of RRUX instruction
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Commit Message

Jozef Lawrynowicz Jan. 22, 2020, 9:57 p.m.
The MSP430X RRUX instruction (unsigned right shift) is synthesized as the RRC
(rotate right through carry) instruction, but with the ZC (zero carry) bit of
the opcode extention word set.

However, the simulator does not check the ZC bit before executing RRC, which
leads to incorrect simulation of RRUX, if the carry bit in the status register
happens to be set.

The attached patch fixes this by modifying the simulation of RRC, so a 1 is only
shifted into the MSB of the destination if the ZC bit of the extension word is
clear AND the carry bit of the status register is set.

I successfully regtested the GCC testsuite for msp430-elf, and this also fixed
gcc.c-torture/execute/20020108-1.c which was executing incorrectly at -O0.

Committed as obvious.

Patch

From b7dcc42dfde12c3a1ccb7149b3cf8ef2f0992ea3 Mon Sep 17 00:00:00 2001
From: Jozef Lawrynowicz <jozef.l@mittosystems.com>
Date: Wed, 22 Jan 2020 21:44:54 +0000
Subject: [PATCH] MSP430: Fix simulator execution of RRUX instruction

The MSP430X RRUX instruction (unsigned right shift) is synthesized as
the RRC (rotate right through carry) instruction, but with the ZC
(zero carry) bit of the opcode extention word set.

Ensure the carry flag is ignored when the ZC bit is set.

sim/msp430/ChangeLog:

2020-01-22  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* msp430-sim.c (msp430_step_once): Ignore the carry flag when executing
	an RRC instruction, if the ZC bit of the extension word is set.

sim/testsuite/sim/msp430/ChangeLog:

2020-01-22  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* rrux.s: New test.
---
 sim/msp430/ChangeLog               |  5 +++++
 sim/msp430/msp430-sim.c            |  6 ++++--
 sim/testsuite/sim/msp430/ChangeLog |  4 ++++
 sim/testsuite/sim/msp430/rrux.s    | 14 ++++++++++++++
 4 files changed, 27 insertions(+), 2 deletions(-)
 create mode 100644 sim/testsuite/sim/msp430/rrux.s

diff --git a/sim/msp430/ChangeLog b/sim/msp430/ChangeLog
index 324a6fcaf1..0f27982068 100644
--- a/sim/msp430/ChangeLog
+++ b/sim/msp430/ChangeLog
@@ -1,3 +1,8 @@ 
+2020-01-22  Jozef Lawrynowicz  <jozef.l@mittosystems.com>
+
+	* msp430-sim.c (msp430_step_once): Ignore the carry flag when executing
+	an RRC instruction, if the ZC bit of the extension word is set.
+
 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
 
 	* configure: Regenerate.
diff --git a/sim/msp430/msp430-sim.c b/sim/msp430/msp430-sim.c
index cdb8eab71f..e21c8cf6a6 100644
--- a/sim/msp430/msp430-sim.c
+++ b/sim/msp430/msp430-sim.c
@@ -1292,8 +1292,10 @@  msp430_step_once (SIM_DESC sd)
 	  u1 = SRC;
 	  carry_to_use = u1 & 1;
 	  uresult = u1 >> 1;
-	  if (SR & MSP430_FLAG_C)
-	  uresult |= (1 << (opcode->size - 1));
+	  /* If the ZC bit of the opcode is set, it means we are synthesizing
+	     RRUX, so the carry bit must be ignored.  */
+	  if (opcode->zc == 0 && (SR & MSP430_FLAG_C))
+	    uresult |= (1 << (opcode->size - 1));
 	  TRACE_ALU (MSP430_CPU (sd), "RRC: %#x >>= %#x",
 		     u1, uresult);
 	  DEST (uresult);
diff --git a/sim/testsuite/sim/msp430/ChangeLog b/sim/testsuite/sim/msp430/ChangeLog
index 458ee21873..7dc370f0a4 100644
--- a/sim/testsuite/sim/msp430/ChangeLog
+++ b/sim/testsuite/sim/msp430/ChangeLog
@@ -1,3 +1,7 @@ 
+2020-01-22  Jozef Lawrynowicz  <jozef.l@mittosystems.com>
+
+	* rrux.s: New test.
+
 2016-01-05  Nick Clifton  <nickc@redhat.com>
 
 	* testutils.inc (__pass): Use the LMA addresses of the _passmsg
diff --git a/sim/testsuite/sim/msp430/rrux.s b/sim/testsuite/sim/msp430/rrux.s
new file mode 100644
index 0000000000..07fc8d5a8d
--- /dev/null
+++ b/sim/testsuite/sim/msp430/rrux.s
@@ -0,0 +1,14 @@ 
+# check that rrux (synthesized as rrc with ZC bit set) works.
+# mach: msp430
+
+.include "testutils.inc"
+
+	start
+
+	setc		; set the carry bit to ensure ZC bit is obeyed
+	mov.w	#16, r10
+	rrux.w	r10
+	cmp.w	#8, r10
+	jeq 1f
+	fail
+	1: pass
-- 
2.17.1