[v2,1/4] RISC-V: Update the CSR to privilege spec 1.12.

Message ID 1575358697-17241-2-git-send-email-nelson.chu@sifive.com
State Superseded
Headers show
Series
  • [v2,1/4] RISC-V: Update the CSR to privilege spec 1.12.
Related show

Commit Message

Nelson Chu Dec. 3, 2019, 7:38 a.m.
gas/
	* testsuite/gas/riscv/priv-reg.s: Rename to priv-reg-all.s  Update
	the CSR to privilege spec 1.12.
	* testsuite/gas/riscv/priv-reg.d: Likewise.
	* testsuite/gas/riscv/bad-csr.s: Rename to priv-reg-fail-nonexistent.
	* testsuite/gas/riscv/bad-csr.d: Likewise.
	* testsuite/gas/riscv/bad-csr.l: Likewise.
	* testsuite/gas/riscv/satp.s: Deleted.  Duplicate of priv-reg-all.s
	* testsuite/gas/riscv/satp.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.s: Updated.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.

	include/
	* opcode/riscv-opc.h: Update the CSR to privilege spec 1.12.

	gdb/
	* features/riscv/32bit-csr.xml: Regenerated.
	* features/riscv/64bit-csr.xml: Regenerated.
---
 gas/testsuite/gas/riscv/bad-csr.d                  |   3 -
 gas/testsuite/gas/riscv/bad-csr.l                  |   2 -
 gas/testsuite/gas/riscv/bad-csr.s                  |   1 -
 gas/testsuite/gas/riscv/csr-dw-regnums.d           |  52 ++--
 gas/testsuite/gas/riscv/csr-dw-regnums.s           |  53 ++--
 gas/testsuite/gas/riscv/priv-reg-all.d             | 270 +++++++++++++++++++
 gas/testsuite/gas/riscv/priv-reg-all.s             | 295 +++++++++++++++++++++
 .../gas/riscv/priv-reg-fail-nonexistent.d          |   3 +
 .../gas/riscv/priv-reg-fail-nonexistent.l          |   2 +
 .../gas/riscv/priv-reg-fail-nonexistent.s          |   1 +
 gas/testsuite/gas/riscv/priv-reg.d                 | 253 ------------------
 gas/testsuite/gas/riscv/priv-reg.s                 | 269 -------------------
 gas/testsuite/gas/riscv/satp.d                     |  11 -
 gas/testsuite/gas/riscv/satp.s                     |   3 -
 gdb/features/riscv/32bit-csr.xml                   |  26 +-
 gdb/features/riscv/64bit-csr.xml                   |  26 +-
 include/opcode/riscv-opc.h                         |  83 ++++--
 17 files changed, 735 insertions(+), 618 deletions(-)
 delete mode 100644 gas/testsuite/gas/riscv/bad-csr.d
 delete mode 100644 gas/testsuite/gas/riscv/bad-csr.l
 delete mode 100644 gas/testsuite/gas/riscv/bad-csr.s
 create mode 100644 gas/testsuite/gas/riscv/priv-reg-all.d
 create mode 100644 gas/testsuite/gas/riscv/priv-reg-all.s
 create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
 create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
 create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
 delete mode 100644 gas/testsuite/gas/riscv/priv-reg.d
 delete mode 100644 gas/testsuite/gas/riscv/priv-reg.s
 delete mode 100644 gas/testsuite/gas/riscv/satp.d
 delete mode 100644 gas/testsuite/gas/riscv/satp.s

-- 
2.7.4

Patch

diff --git a/gas/testsuite/gas/riscv/bad-csr.d b/gas/testsuite/gas/riscv/bad-csr.d
deleted file mode 100644
index 6863123..0000000
--- a/gas/testsuite/gas/riscv/bad-csr.d
+++ /dev/null
@@ -1,3 +0,0 @@ 
-#as:
-#source: bad-csr.s
-#error_output: bad-csr.l
diff --git a/gas/testsuite/gas/riscv/bad-csr.l b/gas/testsuite/gas/riscv/bad-csr.l
deleted file mode 100644
index a0bb8a6..0000000
--- a/gas/testsuite/gas/riscv/bad-csr.l
+++ /dev/null
@@ -1,2 +0,0 @@ 
-.*: Assembler messages:
-.*: Error: unknown CSR `nonexistent'
diff --git a/gas/testsuite/gas/riscv/bad-csr.s b/gas/testsuite/gas/riscv/bad-csr.s
deleted file mode 100644
index 6e6d27e..0000000
--- a/gas/testsuite/gas/riscv/bad-csr.s
+++ /dev/null
@@ -1 +0,0 @@ 
-	csrr a0, nonexistent
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index 597747c..14d1300 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -104,6 +104,22 @@  Contents of the .* section:
   DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
   DW_CFA_offset_extended_sf: r4420 \(sip\) at cfa\+1296
   DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
+  DW_CFA_offset_extended_sf: r5632 \(hstatus\) at cfa\+6144
+  DW_CFA_offset_extended_sf: r5634 \(hedeleg\) at cfa\+6152
+  DW_CFA_offset_extended_sf: r5635 \(hideleg\) at cfa\+6156
+  DW_CFA_offset_extended_sf: r5638 \(hcounteren\) at cfa\+6168
+  DW_CFA_offset_extended_sf: r5760 \(hgatp\) at cfa\+6656
+  DW_CFA_offset_extended_sf: r5637 \(htimedelta\) at cfa\+6164
+  DW_CFA_offset_extended_sf: r5653 \(htimedeltah\) at cfa\+6228
+  DW_CFA_offset_extended_sf: r4608 \(vsstatus\) at cfa\+2048
+  DW_CFA_offset_extended_sf: r4612 \(vsie\) at cfa\+2064
+  DW_CFA_offset_extended_sf: r4613 \(vstvec\) at cfa\+2068
+  DW_CFA_offset_extended_sf: r4672 \(vsscratch\) at cfa\+2304
+  DW_CFA_offset_extended_sf: r4673 \(vsepc) at cfa\+2308
+  DW_CFA_offset_extended_sf: r4674 \(vscause\) at cfa\+2312
+  DW_CFA_offset_extended_sf: r4675 \(vstval\) at cfa\+2316
+  DW_CFA_offset_extended_sf: r4676 \(vsip\) at cfa\+2320
+  DW_CFA_offset_extended_sf: r4736 \(vsatp\) at cfa\+2560
   DW_CFA_offset_extended_sf: r7953 \(mvendorid\) at cfa\+15428
   DW_CFA_offset_extended_sf: r7954 \(marchid\) at cfa\+15432
   DW_CFA_offset_extended_sf: r7955 \(mimpid\) at cfa\+15436
@@ -202,6 +218,7 @@  Contents of the .* section:
   DW_CFA_offset_extended_sf: r7069 \(mhpmcounter29h\) at cfa\+11892
   DW_CFA_offset_extended_sf: r7070 \(mhpmcounter30h\) at cfa\+11896
   DW_CFA_offset_extended_sf: r7071 \(mhpmcounter31h\) at cfa\+11900
+  DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
   DW_CFA_offset_extended_sf: r4899 \(mhpmevent3\) at cfa\+3212
   DW_CFA_offset_extended_sf: r4900 \(mhpmevent4\) at cfa\+3216
   DW_CFA_offset_extended_sf: r4901 \(mhpmevent5\) at cfa\+3220
@@ -237,29 +254,28 @@  Contents of the .* section:
   DW_CFA_offset_extended_sf: r6051 \(tdata3\) at cfa\+7820
   DW_CFA_offset_extended_sf: r6064 \(dcsr\) at cfa\+7872
   DW_CFA_offset_extended_sf: r6065 \(dpc\) at cfa\+7876
-  DW_CFA_offset_extended_sf: r6066 \(dscratch\) at cfa\+7880
-  DW_CFA_offset_extended_sf: r4608 \(hstatus\) at cfa\+2048
-  DW_CFA_offset_extended_sf: r4610 \(hedeleg\) at cfa\+2056
-  DW_CFA_offset_extended_sf: r4611 \(hideleg\) at cfa\+2060
-  DW_CFA_offset_extended_sf: r4612 \(hie\) at cfa\+2064
-  DW_CFA_offset_extended_sf: r4613 \(htvec\) at cfa\+2068
-  DW_CFA_offset_extended_sf: r4672 \(hscratch\) at cfa\+2304
-  DW_CFA_offset_extended_sf: r4673 \(hepc\) at cfa\+2308
-  DW_CFA_offset_extended_sf: r4674 \(hcause\) at cfa\+2312
-  DW_CFA_offset_extended_sf: r4675 \(hbadaddr\) at cfa\+2316
-  DW_CFA_offset_extended_sf: r4676 \(hip\) at cfa\+2320
+  DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
+  DW_CFA_offset_extended_sf: r6067 \(dscratch1\) at cfa\+7884
+  DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
+  DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
+  DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
+  DW_CFA_offset_extended_sf: r4612 \(vsie\) at cfa\+2064
+  DW_CFA_offset_extended_sf: r4613 \(vstvec\) at cfa\+2068
+  DW_CFA_offset_extended_sf: r4672 \(vsscratch\) at cfa\+2304
+  DW_CFA_offset_extended_sf: r4673 \(vsepc\) at cfa\+2308
+  DW_CFA_offset_extended_sf: r4674 \(vscause\) at cfa\+2312
+  DW_CFA_offset_extended_sf: r4675 \(vstval\) at cfa\+2316
+  DW_CFA_offset_extended_sf: r4676 \(vsip\) at cfa\+2320
+  DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
+  DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
+  DW_CFA_offset_extended_sf: r4897 \(mscounteren\) at cfa\+3204
+  DW_CFA_offset_extended_sf: r4898 \(mhcounteren\) at cfa\+320
   DW_CFA_offset_extended_sf: r4992 \(mbase\) at cfa\+3584
   DW_CFA_offset_extended_sf: r4993 \(mbound\) at cfa\+3588
   DW_CFA_offset_extended_sf: r4994 \(mibase\) at cfa\+3592
   DW_CFA_offset_extended_sf: r4995 \(mibound\) at cfa\+3596
   DW_CFA_offset_extended_sf: r4996 \(mdbase\) at cfa\+3600
   DW_CFA_offset_extended_sf: r4997 \(mdbound\) at cfa\+3604
-  DW_CFA_offset_extended_sf: r4896 \(mucounteren\) at cfa\+3200
-  DW_CFA_offset_extended_sf: r4897 \(mscounteren\) at cfa\+3204
-  DW_CFA_offset_extended_sf: r4898 \(mhcounteren\) at cfa\+3208
-  DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268
-  DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
-  DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
-  DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
+  DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
   DW_CFA_nop
 #...
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
index b29e9da..93f293f 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -94,6 +94,22 @@  _start:
 	.cfi_offset stval, 1292
 	.cfi_offset sip, 1296
 	.cfi_offset satp, 1536
+	.cfi_offset hstatus, 6144
+	.cfi_offset hedeleg, 6152
+	.cfi_offset hideleg, 6156
+	.cfi_offset hcounteren, 6168
+	.cfi_offset hgatp, 6656
+	.cfi_offset htimedelta, 6164
+	.cfi_offset htimedeltah, 6228
+	.cfi_offset vsstatus, 2048
+	.cfi_offset vsie, 2064
+	.cfi_offset vstvec, 2068
+	.cfi_offset vsscratch, 2304
+	.cfi_offset vsepc, 2308
+	.cfi_offset vscause, 2312
+	.cfi_offset vstval, 2316
+	.cfi_offset vsip, 2320
+	.cfi_offset vsatp, 2560
 	.cfi_offset mvendorid, 15428
 	.cfi_offset marchid, 15432
 	.cfi_offset mimpid, 15436
@@ -105,6 +121,7 @@  _start:
 	.cfi_offset mie, 3088
 	.cfi_offset mtvec, 3092
 	.cfi_offset mcounteren, 3096
+	.cfi_offset mstatush, 3136
 	.cfi_offset mscratch, 3328
 	.cfi_offset mepc, 3332
 	.cfi_offset mcause, 3336
@@ -192,6 +209,7 @@  _start:
 	.cfi_offset mhpmcounter29h, 11892
 	.cfi_offset mhpmcounter30h, 11896
 	.cfi_offset mhpmcounter31h, 11900
+	.cfi_offset mcountinhibit, 3200
 	.cfi_offset mhpmevent3, 3212
 	.cfi_offset mhpmevent4, 3216
 	.cfi_offset mhpmevent5, 3220
@@ -227,29 +245,28 @@  _start:
 	.cfi_offset tdata3, 7820
 	.cfi_offset dcsr, 7872
 	.cfi_offset dpc, 7876
-	.cfi_offset dscratch, 7880
-	.cfi_offset hstatus, 2048
-	.cfi_offset hedeleg, 2056
-	.cfi_offset hideleg, 2060
-	.cfi_offset hie, 2064
-	.cfi_offset htvec, 2068
-	.cfi_offset hscratch, 2304
-	.cfi_offset hepc, 2308
-	.cfi_offset hcause, 2312
-	.cfi_offset hbadaddr, 2316
-	.cfi_offset hip, 2320
+	.cfi_offset dscratch0, 7880
+	.cfi_offset dscratch1, 7884
+	.cfi_offset ubadaddr, 268	# utval
+	.cfi_offset sbadaddr, 1292	# stval
+	.cfi_offset sptbr, 1536		# satp
+	.cfi_offset hie, 2064		# vsie
+	.cfi_offset htvec, 2068		# vstvec
+	.cfi_offset hscratch, 2304	# vsscratch
+	.cfi_offset hepc, 2308		# vsepc
+	.cfi_offset hcause, 2312	# vscause
+	.cfi_offset hbadaddr, 2316	# vstval
+	.cfi_offset hip, 2320		# vsip
+	.cfi_offset mbadaddr, 3340	# mtval
+	.cfi_offset mucounteren, 3200	# mcountinhibit
+	.cfi_offset mscounteren, 3204
+	.cfi_offset mhcounteren, 3208
 	.cfi_offset mbase, 3584
 	.cfi_offset mbound, 3588
 	.cfi_offset mibase, 3592
 	.cfi_offset mibound, 3596
 	.cfi_offset mdbase, 3600
 	.cfi_offset mdbound, 3604
-	.cfi_offset mucounteren, 3200
-	.cfi_offset mscounteren, 3204
-	.cfi_offset mhcounteren, 3208
-	.cfi_offset ubadaddr, 268
-	.cfi_offset sbadaddr, 1292
-	.cfi_offset sptbr, 1536
-	.cfi_offset mbadaddr, 3340
+	.cfi_offset dscratch, 7880	# dscratch0
 	nop
 	.cfi_endproc
diff --git a/gas/testsuite/gas/riscv/priv-reg-all.d b/gas/testsuite/gas/riscv/priv-reg-all.d
new file mode 100644
index 0000000..d86e8c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-all.d
@@ -0,0 +1,270 @@ 
+#as: -march=rv32if
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+0:[ 	]+00002573[ 	]+csrr[ 	]+a0,ustatus
+.*:[ 	]+00402573[ 	]+csrr[ 	]+a0,uie
+.*:[ 	]+00502573[ 	]+csrr[ 	]+a0,utvec
+.*:[ 	]+04002573[ 	]+csrr[ 	]+a0,uscratch
+.*:[ 	]+04102573[ 	]+csrr[ 	]+a0,uepc
+.*:[ 	]+04202573[ 	]+csrr[ 	]+a0,ucause
+.*:[ 	]+04302573[ 	]+csrr[ 	]+a0,utval
+.*:[ 	]+04402573[ 	]+csrr[ 	]+a0,uip
+.*:[ 	]+00102573[ 	]+frflags[ 	]+a0
+.*:[ 	]+00202573[ 	]+frrm[ 	]+a0
+.*:[ 	]+00302573[ 	]+frcsr[ 	]+a0
+.*:[ 	]+c0002573[ 	]+rdcycle[ 	]+a0
+.*:[ 	]+c0102573[ 	]+rdtime[ 	]+a0
+.*:[ 	]+c0202573[ 	]+rdinstret[ 	]+a0
+.*:[ 	]+c0302573[ 	]+csrr[ 	]+a0,hpmcounter3
+.*:[ 	]+c0402573[ 	]+csrr[ 	]+a0,hpmcounter4
+.*:[ 	]+c0502573[ 	]+csrr[ 	]+a0,hpmcounter5
+.*:[ 	]+c0602573[ 	]+csrr[ 	]+a0,hpmcounter6
+.*:[ 	]+c0702573[ 	]+csrr[ 	]+a0,hpmcounter7
+.*:[ 	]+c0802573[ 	]+csrr[ 	]+a0,hpmcounter8
+.*:[ 	]+c0902573[ 	]+csrr[ 	]+a0,hpmcounter9
+.*:[ 	]+c0a02573[ 	]+csrr[ 	]+a0,hpmcounter10
+.*:[ 	]+c0b02573[ 	]+csrr[ 	]+a0,hpmcounter11
+.*:[ 	]+c0c02573[ 	]+csrr[ 	]+a0,hpmcounter12
+.*:[ 	]+c0d02573[ 	]+csrr[ 	]+a0,hpmcounter13
+.*:[ 	]+c0e02573[ 	]+csrr[ 	]+a0,hpmcounter14
+.*:[ 	]+c0f02573[ 	]+csrr[ 	]+a0,hpmcounter15
+.*:[ 	]+c1002573[ 	]+csrr[ 	]+a0,hpmcounter16
+.*:[ 	]+c1102573[ 	]+csrr[ 	]+a0,hpmcounter17
+.*:[ 	]+c1202573[ 	]+csrr[ 	]+a0,hpmcounter18
+.*:[ 	]+c1302573[ 	]+csrr[ 	]+a0,hpmcounter19
+.*:[ 	]+c1402573[ 	]+csrr[ 	]+a0,hpmcounter20
+.*:[ 	]+c1502573[ 	]+csrr[ 	]+a0,hpmcounter21
+.*:[ 	]+c1602573[ 	]+csrr[ 	]+a0,hpmcounter22
+.*:[ 	]+c1702573[ 	]+csrr[ 	]+a0,hpmcounter23
+.*:[ 	]+c1802573[ 	]+csrr[ 	]+a0,hpmcounter24
+.*:[ 	]+c1902573[ 	]+csrr[ 	]+a0,hpmcounter25
+.*:[ 	]+c1a02573[ 	]+csrr[ 	]+a0,hpmcounter26
+.*:[ 	]+c1b02573[ 	]+csrr[ 	]+a0,hpmcounter27
+.*:[ 	]+c1c02573[ 	]+csrr[ 	]+a0,hpmcounter28
+.*:[ 	]+c1d02573[ 	]+csrr[ 	]+a0,hpmcounter29
+.*:[ 	]+c1e02573[ 	]+csrr[ 	]+a0,hpmcounter30
+.*:[ 	]+c1f02573[ 	]+csrr[ 	]+a0,hpmcounter31
+.*:[ 	]+c8002573[ 	]+rdcycleh[ 	]+a0
+.*:[ 	]+c8102573[ 	]+rdtimeh[ 	]+a0
+.*:[ 	]+c8202573[ 	]+rdinstreth[ 	]+a0
+.*:[ 	]+c8302573[ 	]+csrr[ 	]+a0,hpmcounter3h
+.*:[ 	]+c8402573[ 	]+csrr[ 	]+a0,hpmcounter4h
+.*:[ 	]+c8502573[ 	]+csrr[ 	]+a0,hpmcounter5h
+.*:[ 	]+c8602573[ 	]+csrr[ 	]+a0,hpmcounter6h
+.*:[ 	]+c8702573[ 	]+csrr[ 	]+a0,hpmcounter7h
+.*:[ 	]+c8802573[ 	]+csrr[ 	]+a0,hpmcounter8h
+.*:[ 	]+c8902573[ 	]+csrr[ 	]+a0,hpmcounter9h
+.*:[ 	]+c8a02573[ 	]+csrr[ 	]+a0,hpmcounter10h
+.*:[ 	]+c8b02573[ 	]+csrr[ 	]+a0,hpmcounter11h
+.*:[ 	]+c8c02573[ 	]+csrr[ 	]+a0,hpmcounter12h
+.*:[ 	]+c8d02573[ 	]+csrr[ 	]+a0,hpmcounter13h
+.*:[ 	]+c8e02573[ 	]+csrr[ 	]+a0,hpmcounter14h
+.*:[ 	]+c8f02573[ 	]+csrr[ 	]+a0,hpmcounter15h
+.*:[ 	]+c9002573[ 	]+csrr[ 	]+a0,hpmcounter16h
+.*:[ 	]+c9102573[ 	]+csrr[ 	]+a0,hpmcounter17h
+.*:[ 	]+c9202573[ 	]+csrr[ 	]+a0,hpmcounter18h
+.*:[ 	]+c9302573[ 	]+csrr[ 	]+a0,hpmcounter19h
+.*:[ 	]+c9402573[ 	]+csrr[ 	]+a0,hpmcounter20h
+.*:[ 	]+c9502573[ 	]+csrr[ 	]+a0,hpmcounter21h
+.*:[ 	]+c9602573[ 	]+csrr[ 	]+a0,hpmcounter22h
+.*:[ 	]+c9702573[ 	]+csrr[ 	]+a0,hpmcounter23h
+.*:[ 	]+c9802573[ 	]+csrr[ 	]+a0,hpmcounter24h
+.*:[ 	]+c9902573[ 	]+csrr[ 	]+a0,hpmcounter25h
+.*:[ 	]+c9a02573[ 	]+csrr[ 	]+a0,hpmcounter26h
+.*:[ 	]+c9b02573[ 	]+csrr[ 	]+a0,hpmcounter27h
+.*:[ 	]+c9c02573[ 	]+csrr[ 	]+a0,hpmcounter28h
+.*:[ 	]+c9d02573[ 	]+csrr[ 	]+a0,hpmcounter29h
+.*:[ 	]+c9e02573[ 	]+csrr[ 	]+a0,hpmcounter30h
+.*:[ 	]+c9f02573[ 	]+csrr[ 	]+a0,hpmcounter31h
+.*:[ 	]+10002573[ 	]+csrr[ 	]+a0,sstatus
+.*:[ 	]+10202573[ 	]+csrr[ 	]+a0,sedeleg
+.*:[ 	]+10302573[ 	]+csrr[ 	]+a0,sideleg
+.*:[ 	]+10402573[ 	]+csrr[ 	]+a0,sie
+.*:[ 	]+10502573[ 	]+csrr[ 	]+a0,stvec
+.*:[ 	]+10602573[ 	]+csrr[ 	]+a0,scounteren
+.*:[ 	]+14002573[ 	]+csrr[ 	]+a0,sscratch
+.*:[ 	]+14102573[ 	]+csrr[ 	]+a0,sepc
+.*:[ 	]+14202573[ 	]+csrr[ 	]+a0,scause
+.*:[ 	]+14302573[ 	]+csrr[ 	]+a0,stval
+.*:[ 	]+14402573[ 	]+csrr[ 	]+a0,sip
+.*:[ 	]+18002573[ 	]+csrr[ 	]+a0,satp
+.*:[ 	]+60002573[ 	]+csrr[ 	]+a0,hstatus
+.*:[ 	]+60202573[ 	]+csrr[ 	]+a0,hedeleg
+.*:[ 	]+60302573[ 	]+csrr[ 	]+a0,hideleg
+.*:[ 	]+60602573[ 	]+csrr[ 	]+a0,hcounteren
+.*:[ 	]+68002573[ 	]+csrr[ 	]+a0,hgatp
+.*:[ 	]+60502573[ 	]+csrr[ 	]+a0,htimedelta
+.*:[ 	]+61502573[ 	]+csrr[ 	]+a0,htimedeltah
+.*:[ 	]+20002573[ 	]+csrr[ 	]+a0,vsstatus
+.*:[ 	]+20402573[ 	]+csrr[ 	]+a0,vsie
+.*:[ 	]+20502573[ 	]+csrr[ 	]+a0,vstvec
+.*:[ 	]+24002573[ 	]+csrr[ 	]+a0,vsscratch
+.*:[ 	]+24102573[ 	]+csrr[ 	]+a0,vsepc
+.*:[ 	]+24202573[ 	]+csrr[ 	]+a0,vscause
+.*:[ 	]+24302573[ 	]+csrr[ 	]+a0,vstval
+.*:[ 	]+24402573[ 	]+csrr[ 	]+a0,vsip
+.*:[ 	]+28002573[ 	]+csrr[ 	]+a0,vsatp
+.*:[ 	]+f1102573[ 	]+csrr[ 	]+a0,mvendorid
+.*:[ 	]+f1202573[ 	]+csrr[ 	]+a0,marchid
+.*:[ 	]+f1302573[ 	]+csrr[ 	]+a0,mimpid
+.*:[ 	]+f1402573[ 	]+csrr[ 	]+a0,mhartid
+.*:[ 	]+30002573[ 	]+csrr[ 	]+a0,mstatus
+.*:[ 	]+30102573[ 	]+csrr[ 	]+a0,misa
+.*:[ 	]+30202573[ 	]+csrr[ 	]+a0,medeleg
+.*:[ 	]+30302573[ 	]+csrr[ 	]+a0,mideleg
+.*:[ 	]+30402573[ 	]+csrr[ 	]+a0,mie
+.*:[ 	]+30502573[ 	]+csrr[ 	]+a0,mtvec
+.*:[ 	]+30602573[ 	]+csrr[ 	]+a0,mcounteren
+.*:[ 	]+31002573[ 	]+csrr[ 	]+a0,mstatush
+.*:[ 	]+34002573[ 	]+csrr[ 	]+a0,mscratch
+.*:[ 	]+34102573[ 	]+csrr[ 	]+a0,mepc
+.*:[ 	]+34202573[ 	]+csrr[ 	]+a0,mcause
+.*:[ 	]+34302573[ 	]+csrr[ 	]+a0,mtval
+.*:[ 	]+34402573[ 	]+csrr[ 	]+a0,mip
+.*:[ 	]+3a002573[ 	]+csrr[ 	]+a0,pmpcfg0
+.*:[ 	]+3a102573[ 	]+csrr[ 	]+a0,pmpcfg1
+.*:[ 	]+3a202573[ 	]+csrr[ 	]+a0,pmpcfg2
+.*:[ 	]+3a302573[ 	]+csrr[ 	]+a0,pmpcfg3
+.*:[ 	]+3b002573[ 	]+csrr[ 	]+a0,pmpaddr0
+.*:[ 	]+3b102573[ 	]+csrr[ 	]+a0,pmpaddr1
+.*:[ 	]+3b202573[ 	]+csrr[ 	]+a0,pmpaddr2
+.*:[ 	]+3b302573[ 	]+csrr[ 	]+a0,pmpaddr3
+.*:[ 	]+3b402573[ 	]+csrr[ 	]+a0,pmpaddr4
+.*:[ 	]+3b502573[ 	]+csrr[ 	]+a0,pmpaddr5
+.*:[ 	]+3b602573[ 	]+csrr[ 	]+a0,pmpaddr6
+.*:[ 	]+3b702573[ 	]+csrr[ 	]+a0,pmpaddr7
+.*:[ 	]+3b802573[ 	]+csrr[ 	]+a0,pmpaddr8
+.*:[ 	]+3b902573[ 	]+csrr[ 	]+a0,pmpaddr9
+.*:[ 	]+3ba02573[ 	]+csrr[ 	]+a0,pmpaddr10
+.*:[ 	]+3bb02573[ 	]+csrr[ 	]+a0,pmpaddr11
+.*:[ 	]+3bc02573[ 	]+csrr[ 	]+a0,pmpaddr12
+.*:[ 	]+3bd02573[ 	]+csrr[ 	]+a0,pmpaddr13
+.*:[ 	]+3be02573[ 	]+csrr[ 	]+a0,pmpaddr14
+.*:[ 	]+3bf02573[ 	]+csrr[ 	]+a0,pmpaddr15
+.*:[ 	]+b0002573[ 	]+csrr[ 	]+a0,mcycle
+.*:[ 	]+b0202573[ 	]+csrr[ 	]+a0,minstret
+.*:[ 	]+b0302573[ 	]+csrr[ 	]+a0,mhpmcounter3
+.*:[ 	]+b0402573[ 	]+csrr[ 	]+a0,mhpmcounter4
+.*:[ 	]+b0502573[ 	]+csrr[ 	]+a0,mhpmcounter5
+.*:[ 	]+b0602573[ 	]+csrr[ 	]+a0,mhpmcounter6
+.*:[ 	]+b0702573[ 	]+csrr[ 	]+a0,mhpmcounter7
+.*:[ 	]+b0802573[ 	]+csrr[ 	]+a0,mhpmcounter8
+.*:[ 	]+b0902573[ 	]+csrr[ 	]+a0,mhpmcounter9
+.*:[ 	]+b0a02573[ 	]+csrr[ 	]+a0,mhpmcounter10
+.*:[ 	]+b0b02573[ 	]+csrr[ 	]+a0,mhpmcounter11
+.*:[ 	]+b0c02573[ 	]+csrr[ 	]+a0,mhpmcounter12
+.*:[ 	]+b0d02573[ 	]+csrr[ 	]+a0,mhpmcounter13
+.*:[ 	]+b0e02573[ 	]+csrr[ 	]+a0,mhpmcounter14
+.*:[ 	]+b0f02573[ 	]+csrr[ 	]+a0,mhpmcounter15
+.*:[ 	]+b1002573[ 	]+csrr[ 	]+a0,mhpmcounter16
+.*:[ 	]+b1102573[ 	]+csrr[ 	]+a0,mhpmcounter17
+.*:[ 	]+b1202573[ 	]+csrr[ 	]+a0,mhpmcounter18
+.*:[ 	]+b1302573[ 	]+csrr[ 	]+a0,mhpmcounter19
+.*:[ 	]+b1402573[ 	]+csrr[ 	]+a0,mhpmcounter20
+.*:[ 	]+b1502573[ 	]+csrr[ 	]+a0,mhpmcounter21
+.*:[ 	]+b1602573[ 	]+csrr[ 	]+a0,mhpmcounter22
+.*:[ 	]+b1702573[ 	]+csrr[ 	]+a0,mhpmcounter23
+.*:[ 	]+b1802573[ 	]+csrr[ 	]+a0,mhpmcounter24
+.*:[ 	]+b1902573[ 	]+csrr[ 	]+a0,mhpmcounter25
+.*:[ 	]+b1a02573[ 	]+csrr[ 	]+a0,mhpmcounter26
+.*:[ 	]+b1b02573[ 	]+csrr[ 	]+a0,mhpmcounter27
+.*:[ 	]+b1c02573[ 	]+csrr[ 	]+a0,mhpmcounter28
+.*:[ 	]+b1d02573[ 	]+csrr[ 	]+a0,mhpmcounter29
+.*:[ 	]+b1e02573[ 	]+csrr[ 	]+a0,mhpmcounter30
+.*:[ 	]+b1f02573[ 	]+csrr[ 	]+a0,mhpmcounter31
+.*:[ 	]+b8002573[ 	]+csrr[ 	]+a0,mcycleh
+.*:[ 	]+b8202573[ 	]+csrr[ 	]+a0,minstreth
+.*:[ 	]+b8302573[ 	]+csrr[ 	]+a0,mhpmcounter3h
+.*:[ 	]+b8402573[ 	]+csrr[ 	]+a0,mhpmcounter4h
+.*:[ 	]+b8502573[ 	]+csrr[ 	]+a0,mhpmcounter5h
+.*:[ 	]+b8602573[ 	]+csrr[ 	]+a0,mhpmcounter6h
+.*:[ 	]+b8702573[ 	]+csrr[ 	]+a0,mhpmcounter7h
+.*:[ 	]+b8802573[ 	]+csrr[ 	]+a0,mhpmcounter8h
+.*:[ 	]+b8902573[ 	]+csrr[ 	]+a0,mhpmcounter9h
+.*:[ 	]+b8a02573[ 	]+csrr[ 	]+a0,mhpmcounter10h
+.*:[ 	]+b8b02573[ 	]+csrr[ 	]+a0,mhpmcounter11h
+.*:[ 	]+b8c02573[ 	]+csrr[ 	]+a0,mhpmcounter12h
+.*:[ 	]+b8d02573[ 	]+csrr[ 	]+a0,mhpmcounter13h
+.*:[ 	]+b8e02573[ 	]+csrr[ 	]+a0,mhpmcounter14h
+.*:[ 	]+b8f02573[ 	]+csrr[ 	]+a0,mhpmcounter15h
+.*:[ 	]+b9002573[ 	]+csrr[ 	]+a0,mhpmcounter16h
+.*:[ 	]+b9102573[ 	]+csrr[ 	]+a0,mhpmcounter17h
+.*:[ 	]+b9202573[ 	]+csrr[ 	]+a0,mhpmcounter18h
+.*:[ 	]+b9302573[ 	]+csrr[ 	]+a0,mhpmcounter19h
+.*:[ 	]+b9402573[ 	]+csrr[ 	]+a0,mhpmcounter20h
+.*:[ 	]+b9502573[ 	]+csrr[ 	]+a0,mhpmcounter21h
+.*:[ 	]+b9602573[ 	]+csrr[ 	]+a0,mhpmcounter22h
+.*:[ 	]+b9702573[ 	]+csrr[ 	]+a0,mhpmcounter23h
+.*:[ 	]+b9802573[ 	]+csrr[ 	]+a0,mhpmcounter24h
+.*:[ 	]+b9902573[ 	]+csrr[ 	]+a0,mhpmcounter25h
+.*:[ 	]+b9a02573[ 	]+csrr[ 	]+a0,mhpmcounter26h
+.*:[ 	]+b9b02573[ 	]+csrr[ 	]+a0,mhpmcounter27h
+.*:[ 	]+b9c02573[ 	]+csrr[ 	]+a0,mhpmcounter28h
+.*:[ 	]+b9d02573[ 	]+csrr[ 	]+a0,mhpmcounter29h
+.*:[ 	]+b9e02573[ 	]+csrr[ 	]+a0,mhpmcounter30h
+.*:[ 	]+b9f02573[ 	]+csrr[ 	]+a0,mhpmcounter31h
+.*:[ 	]+32002573[ 	]+csrr[ 	]+a0,mcountinhibit
+.*:[ 	]+32302573[ 	]+csrr[ 	]+a0,mhpmevent3
+.*:[ 	]+32402573[ 	]+csrr[ 	]+a0,mhpmevent4
+.*:[ 	]+32502573[ 	]+csrr[ 	]+a0,mhpmevent5
+.*:[ 	]+32602573[ 	]+csrr[ 	]+a0,mhpmevent6
+.*:[ 	]+32702573[ 	]+csrr[ 	]+a0,mhpmevent7
+.*:[ 	]+32802573[ 	]+csrr[ 	]+a0,mhpmevent8
+.*:[ 	]+32902573[ 	]+csrr[ 	]+a0,mhpmevent9
+.*:[ 	]+32a02573[ 	]+csrr[ 	]+a0,mhpmevent10
+.*:[ 	]+32b02573[ 	]+csrr[ 	]+a0,mhpmevent11
+.*:[ 	]+32c02573[ 	]+csrr[ 	]+a0,mhpmevent12
+.*:[ 	]+32d02573[ 	]+csrr[ 	]+a0,mhpmevent13
+.*:[ 	]+32e02573[ 	]+csrr[ 	]+a0,mhpmevent14
+.*:[ 	]+32f02573[ 	]+csrr[ 	]+a0,mhpmevent15
+.*:[ 	]+33002573[ 	]+csrr[ 	]+a0,mhpmevent16
+.*:[ 	]+33102573[ 	]+csrr[ 	]+a0,mhpmevent17
+.*:[ 	]+33202573[ 	]+csrr[ 	]+a0,mhpmevent18
+.*:[ 	]+33302573[ 	]+csrr[ 	]+a0,mhpmevent19
+.*:[ 	]+33402573[ 	]+csrr[ 	]+a0,mhpmevent20
+.*:[ 	]+33502573[ 	]+csrr[ 	]+a0,mhpmevent21
+.*:[ 	]+33602573[ 	]+csrr[ 	]+a0,mhpmevent22
+.*:[ 	]+33702573[ 	]+csrr[ 	]+a0,mhpmevent23
+.*:[ 	]+33802573[ 	]+csrr[ 	]+a0,mhpmevent24
+.*:[ 	]+33902573[ 	]+csrr[ 	]+a0,mhpmevent25
+.*:[ 	]+33a02573[ 	]+csrr[ 	]+a0,mhpmevent26
+.*:[ 	]+33b02573[ 	]+csrr[ 	]+a0,mhpmevent27
+.*:[ 	]+33c02573[ 	]+csrr[ 	]+a0,mhpmevent28
+.*:[ 	]+33d02573[ 	]+csrr[ 	]+a0,mhpmevent29
+.*:[ 	]+33e02573[ 	]+csrr[ 	]+a0,mhpmevent30
+.*:[ 	]+33f02573[ 	]+csrr[ 	]+a0,mhpmevent31
+.*:[ 	]+7a002573[ 	]+csrr[ 	]+a0,tselect
+.*:[ 	]+7a102573[ 	]+csrr[ 	]+a0,tdata1
+.*:[ 	]+7a202573[ 	]+csrr[ 	]+a0,tdata2
+.*:[ 	]+7a302573[ 	]+csrr[ 	]+a0,tdata3
+.*:[ 	]+7b002573[ 	]+csrr[ 	]+a0,dcsr
+.*:[ 	]+7b102573[ 	]+csrr[ 	]+a0,dpc
+.*:[ 	]+7b202573[ 	]+csrr[ 	]+a0,dscratch0
+.*:[ 	]+7b302573[ 	]+csrr[ 	]+a0,dscratch1
+.*:[ 	]+04302573[ 	]+csrr[ 	]+a0,utval
+.*:[ 	]+14302573[ 	]+csrr[ 	]+a0,stval
+.*:[ 	]+18002573[ 	]+csrr[ 	]+a0,satp
+.*:[ 	]+20402573[ 	]+csrr[ 	]+a0,vsie
+.*:[ 	]+20502573[ 	]+csrr[ 	]+a0,vstvec
+.*:[ 	]+24002573[ 	]+csrr[ 	]+a0,vsscratch
+.*:[ 	]+24102573[ 	]+csrr[ 	]+a0,vsepc
+.*:[ 	]+24202573[ 	]+csrr[ 	]+a0,vscause
+.*:[ 	]+24302573[ 	]+csrr[ 	]+a0,vstval
+.*:[ 	]+24402573[ 	]+csrr[ 	]+a0,vsip
+.*:[ 	]+34302573[ 	]+csrr[ 	]+a0,mtval
+.*:[ 	]+32002573[ 	]+csrr[ 	]+a0,mcountinhibit
+.*:[ 	]+32102573[ 	]+csrr[ 	]+a0,mscounteren
+.*:[ 	]+32202573[ 	]+csrr[ 	]+a0,mhcounteren
+.*:[ 	]+38002573[ 	]+csrr[ 	]+a0,mbase
+.*:[ 	]+38102573[ 	]+csrr[ 	]+a0,mbound
+.*:[ 	]+38202573[ 	]+csrr[ 	]+a0,mibase
+.*:[ 	]+38302573[ 	]+csrr[ 	]+a0,mibound
+.*:[ 	]+38402573[ 	]+csrr[ 	]+a0,mdbase
+.*:[ 	]+38502573[ 	]+csrr[ 	]+a0,mdbound
+.*:[ 	]+7b202573[ 	]+csrr[ 	]+a0,dscratch0
diff --git a/gas/testsuite/gas/riscv/priv-reg-all.s b/gas/testsuite/gas/riscv/priv-reg-all.s
new file mode 100644
index 0000000..4dc6716
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-all.s
@@ -0,0 +1,295 @@ 
+# From priv spec 1.9.1 to 1.12 registers.
+
+	.macro csr val
+	csrr a0,\val
+	.endm
+
+# User-Level CSR Addresses in 1.12.
+	csr ustatus
+	csr uie
+	csr utvec
+
+	csr uscratch
+	csr uepc
+	csr ucause
+	csr utval
+	csr uip
+
+	csr fflags
+	csr frm
+	csr fcsr
+
+	csr cycle
+	csr time
+	csr instret
+	csr hpmcounter3
+	csr hpmcounter4
+	csr hpmcounter5
+	csr hpmcounter6
+	csr hpmcounter7
+	csr hpmcounter8
+	csr hpmcounter9
+	csr hpmcounter10
+	csr hpmcounter11
+	csr hpmcounter12
+	csr hpmcounter13
+	csr hpmcounter14
+	csr hpmcounter15
+	csr hpmcounter16
+	csr hpmcounter17
+	csr hpmcounter18
+	csr hpmcounter19
+	csr hpmcounter20
+	csr hpmcounter21
+	csr hpmcounter22
+	csr hpmcounter23
+	csr hpmcounter24
+	csr hpmcounter25
+	csr hpmcounter26
+	csr hpmcounter27
+	csr hpmcounter28
+	csr hpmcounter29
+	csr hpmcounter30
+	csr hpmcounter31
+	csr cycleh
+	csr timeh
+	csr instreth
+	csr hpmcounter3h
+	csr hpmcounter4h
+	csr hpmcounter5h
+	csr hpmcounter6h
+	csr hpmcounter7h
+	csr hpmcounter8h
+	csr hpmcounter9h
+	csr hpmcounter10h
+	csr hpmcounter11h
+	csr hpmcounter12h
+	csr hpmcounter13h
+	csr hpmcounter14h
+	csr hpmcounter15h
+	csr hpmcounter16h
+	csr hpmcounter17h
+	csr hpmcounter18h
+	csr hpmcounter19h
+	csr hpmcounter20h
+	csr hpmcounter21h
+	csr hpmcounter22h
+	csr hpmcounter23h
+	csr hpmcounter24h
+	csr hpmcounter25h
+	csr hpmcounter26h
+	csr hpmcounter27h
+	csr hpmcounter28h
+	csr hpmcounter29h
+	csr hpmcounter30h
+	csr hpmcounter31h
+
+# Supervisor-level CSR Addresses in 1.12.
+	csr sstatus
+	csr sedeleg
+	csr sideleg
+	csr sie
+	csr stvec
+	csr scounteren
+
+	csr sscratch
+	csr sepc
+	csr scause
+	csr stval
+	csr sip
+
+	csr satp
+
+# Hypervisor-Level CSR Addresses in 1.12.
+	csr hstatus
+	csr hedeleg
+	csr hideleg
+	csr hcounteren
+
+	csr hgatp
+
+	csr htimedelta
+	csr htimedeltah
+
+	csr vsstatus
+	csr vsie
+	csr vstvec
+	csr vsscratch
+	csr vsepc
+	csr vscause
+	csr vstval
+	csr vsip
+	csr vsatp
+
+# Machine-Level CSR Addresses in 1.12.
+	csr mvendorid
+	csr marchid
+	csr mimpid
+	csr mhartid
+
+	csr mstatus
+	csr misa
+	csr medeleg
+	csr mideleg
+	csr mie
+	csr mtvec
+	csr mcounteren
+	csr mstatush
+
+	csr mscratch
+	csr mepc
+	csr mcause
+	csr mtval
+	csr mip
+
+	csr pmpcfg0
+	csr pmpcfg1
+	csr pmpcfg2
+	csr pmpcfg3
+	csr pmpaddr0
+	csr pmpaddr1
+	csr pmpaddr2
+	csr pmpaddr3
+	csr pmpaddr4
+	csr pmpaddr5
+	csr pmpaddr6
+	csr pmpaddr7
+	csr pmpaddr8
+	csr pmpaddr9
+	csr pmpaddr10
+	csr pmpaddr11
+	csr pmpaddr12
+	csr pmpaddr13
+	csr pmpaddr14
+	csr pmpaddr15
+
+	csr mcycle
+	csr minstret
+	csr mhpmcounter3
+	csr mhpmcounter4
+	csr mhpmcounter5
+	csr mhpmcounter6
+	csr mhpmcounter7
+	csr mhpmcounter8
+	csr mhpmcounter9
+	csr mhpmcounter10
+	csr mhpmcounter11
+	csr mhpmcounter12
+	csr mhpmcounter13
+	csr mhpmcounter14
+	csr mhpmcounter15
+	csr mhpmcounter16
+	csr mhpmcounter17
+	csr mhpmcounter18
+	csr mhpmcounter19
+	csr mhpmcounter20
+	csr mhpmcounter21
+	csr mhpmcounter22
+	csr mhpmcounter23
+	csr mhpmcounter24
+	csr mhpmcounter25
+	csr mhpmcounter26
+	csr mhpmcounter27
+	csr mhpmcounter28
+	csr mhpmcounter29
+	csr mhpmcounter30
+	csr mhpmcounter31
+	csr mcycleh
+	csr minstreth
+	csr mhpmcounter3h
+	csr mhpmcounter4h
+	csr mhpmcounter5h
+	csr mhpmcounter6h
+	csr mhpmcounter7h
+	csr mhpmcounter8h
+	csr mhpmcounter9h
+	csr mhpmcounter10h
+	csr mhpmcounter11h
+	csr mhpmcounter12h
+	csr mhpmcounter13h
+	csr mhpmcounter14h
+	csr mhpmcounter15h
+	csr mhpmcounter16h
+	csr mhpmcounter17h
+	csr mhpmcounter18h
+	csr mhpmcounter19h
+	csr mhpmcounter20h
+	csr mhpmcounter21h
+	csr mhpmcounter22h
+	csr mhpmcounter23h
+	csr mhpmcounter24h
+	csr mhpmcounter25h
+	csr mhpmcounter26h
+	csr mhpmcounter27h
+	csr mhpmcounter28h
+	csr mhpmcounter29h
+	csr mhpmcounter30h
+	csr mhpmcounter31h
+
+	csr mcountinhibit
+	csr mhpmevent3
+	csr mhpmevent4
+	csr mhpmevent5
+	csr mhpmevent6
+	csr mhpmevent7
+	csr mhpmevent8
+	csr mhpmevent9
+	csr mhpmevent10
+	csr mhpmevent11
+	csr mhpmevent12
+	csr mhpmevent13
+	csr mhpmevent14
+	csr mhpmevent15
+	csr mhpmevent16
+	csr mhpmevent17
+	csr mhpmevent18
+	csr mhpmevent19
+	csr mhpmevent20
+	csr mhpmevent21
+	csr mhpmevent22
+	csr mhpmevent23
+	csr mhpmevent24
+	csr mhpmevent25
+	csr mhpmevent26
+	csr mhpmevent27
+	csr mhpmevent28
+	csr mhpmevent29
+	csr mhpmevent30
+	csr mhpmevent31
+
+	csr tselect
+	csr tdata1
+	csr tdata2
+	csr tdata3
+
+	csr dcsr
+	csr dpc
+	csr dscratch0
+	csr dscratch1
+
+# Defined in 1.9.1, but alias for another CSR in 1.12.
+	csr ubadaddr	# utval
+	csr sbadaddr	# stval
+	csr sptbr	# satp
+	csr hie		# vsie
+	csr htvec	# vstvec
+	csr hscratch	# vsscratch
+	csr hepc	# vsepc
+	csr hcause	# vscause
+	csr hbadaddr	# vstval
+	csr hip		# vsip
+	csr mbadaddr	# mtval
+	csr mucounteren	# mcountinhibit
+
+# Defined in 1.9.1, but dropped in 1.10.
+	csr mscounteren
+	csr mhcounteren
+	csr mbase
+	csr mbound
+	csr mibase
+	csr mibound
+	csr mdbase
+	csr mdbound
+
+# Defined in 1.10, but dropped in 1.12.
+	csr dscratch	# dscratch0
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
new file mode 100644
index 0000000..9bb3f82
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
@@ -0,0 +1,3 @@ 
+#as:
+#source: priv-reg-fail-nonexistent.s
+#error_output: priv-reg-fail-nonexistent.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
new file mode 100644
index 0000000..a0bb8a6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
@@ -0,0 +1,2 @@ 
+.*: Assembler messages:
+.*: Error: unknown CSR `nonexistent'
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
new file mode 100644
index 0000000..6e6d27e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
@@ -0,0 +1 @@ 
+	csrr a0, nonexistent
diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
deleted file mode 100644
index d8ec868..0000000
--- a/gas/testsuite/gas/riscv/priv-reg.d
+++ /dev/null
@@ -1,253 +0,0 @@ 
-#as: -march=rv32i
-#objdump: -dr
-
-.*:[ 	]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <.text>:
-[ 	]+0:[ 	]+00002573[ 	]+csrr[ 	]+a0,ustatus
-[ 	]+4:[ 	]+00402573[ 	]+csrr[ 	]+a0,uie
-[ 	]+8:[ 	]+00502573[ 	]+csrr[ 	]+a0,utvec
-[ 	]+c:[ 	]+04002573[ 	]+csrr[ 	]+a0,uscratch
-[ 	]+10:[ 	]+04102573[ 	]+csrr[ 	]+a0,uepc
-[ 	]+14:[ 	]+04202573[ 	]+csrr[ 	]+a0,ucause
-[ 	]+18:[ 	]+04302573[ 	]+csrr[ 	]+a0,utval
-[ 	]+1c:[ 	]+04402573[ 	]+csrr[ 	]+a0,uip
-[ 	]+20:[ 	]+00102573[ 	]+frflags[ 	]+a0
-[ 	]+24:[ 	]+00202573[ 	]+frrm[ 	]+a0
-[ 	]+28:[ 	]+00302573[ 	]+frcsr[ 	]+a0
-[ 	]+2c:[ 	]+c0002573[ 	]+rdcycle[ 	]+a0
-[ 	]+30:[ 	]+c0102573[ 	]+rdtime[ 	]+a0
-[ 	]+34:[ 	]+c0202573[ 	]+rdinstret[ 	]+a0
-[ 	]+38:[ 	]+c0302573[ 	]+csrr[ 	]+a0,hpmcounter3
-[ 	]+3c:[ 	]+c0402573[ 	]+csrr[ 	]+a0,hpmcounter4
-[ 	]+40:[ 	]+c0502573[ 	]+csrr[ 	]+a0,hpmcounter5
-[ 	]+44:[ 	]+c0602573[ 	]+csrr[ 	]+a0,hpmcounter6
-[ 	]+48:[ 	]+c0702573[ 	]+csrr[ 	]+a0,hpmcounter7
-[ 	]+4c:[ 	]+c0802573[ 	]+csrr[ 	]+a0,hpmcounter8
-[ 	]+50:[ 	]+c0902573[ 	]+csrr[ 	]+a0,hpmcounter9
-[ 	]+54:[ 	]+c0a02573[ 	]+csrr[ 	]+a0,hpmcounter10
-[ 	]+58:[ 	]+c0b02573[ 	]+csrr[ 	]+a0,hpmcounter11
-[ 	]+5c:[ 	]+c0c02573[ 	]+csrr[ 	]+a0,hpmcounter12
-[ 	]+60:[ 	]+c0d02573[ 	]+csrr[ 	]+a0,hpmcounter13
-[ 	]+64:[ 	]+c0e02573[ 	]+csrr[ 	]+a0,hpmcounter14
-[ 	]+68:[ 	]+c0f02573[ 	]+csrr[ 	]+a0,hpmcounter15
-[ 	]+6c:[ 	]+c1002573[ 	]+csrr[ 	]+a0,hpmcounter16
-[ 	]+70:[ 	]+c1102573[ 	]+csrr[ 	]+a0,hpmcounter17
-[ 	]+74:[ 	]+c1202573[ 	]+csrr[ 	]+a0,hpmcounter18
-[ 	]+78:[ 	]+c1302573[ 	]+csrr[ 	]+a0,hpmcounter19
-[ 	]+7c:[ 	]+c1402573[ 	]+csrr[ 	]+a0,hpmcounter20
-[ 	]+80:[ 	]+c1502573[ 	]+csrr[ 	]+a0,hpmcounter21
-[ 	]+84:[ 	]+c1602573[ 	]+csrr[ 	]+a0,hpmcounter22
-[ 	]+88:[ 	]+c1702573[ 	]+csrr[ 	]+a0,hpmcounter23
-[ 	]+8c:[ 	]+c1802573[ 	]+csrr[ 	]+a0,hpmcounter24
-[ 	]+90:[ 	]+c1902573[ 	]+csrr[ 	]+a0,hpmcounter25
-[ 	]+94:[ 	]+c1a02573[ 	]+csrr[ 	]+a0,hpmcounter26
-[ 	]+98:[ 	]+c1b02573[ 	]+csrr[ 	]+a0,hpmcounter27
-[ 	]+9c:[ 	]+c1c02573[ 	]+csrr[ 	]+a0,hpmcounter28
-[ 	]+a0:[ 	]+c1d02573[ 	]+csrr[ 	]+a0,hpmcounter29
-[ 	]+a4:[ 	]+c1e02573[ 	]+csrr[ 	]+a0,hpmcounter30
-[ 	]+a8:[ 	]+c1f02573[ 	]+csrr[ 	]+a0,hpmcounter31
-[ 	]+ac:[ 	]+c8002573[ 	]+rdcycleh[ 	]+a0
-[ 	]+b0:[ 	]+c8102573[ 	]+rdtimeh[ 	]+a0
-[ 	]+b4:[ 	]+c8202573[ 	]+rdinstreth[ 	]+a0
-[ 	]+b8:[ 	]+c8302573[ 	]+csrr[ 	]+a0,hpmcounter3h
-[ 	]+bc:[ 	]+c8402573[ 	]+csrr[ 	]+a0,hpmcounter4h
-[ 	]+c0:[ 	]+c8502573[ 	]+csrr[ 	]+a0,hpmcounter5h
-[ 	]+c4:[ 	]+c8602573[ 	]+csrr[ 	]+a0,hpmcounter6h
-[ 	]+c8:[ 	]+c8702573[ 	]+csrr[ 	]+a0,hpmcounter7h
-[ 	]+cc:[ 	]+c8802573[ 	]+csrr[ 	]+a0,hpmcounter8h
-[ 	]+d0:[ 	]+c8902573[ 	]+csrr[ 	]+a0,hpmcounter9h
-[ 	]+d4:[ 	]+c8a02573[ 	]+csrr[ 	]+a0,hpmcounter10h
-[ 	]+d8:[ 	]+c8b02573[ 	]+csrr[ 	]+a0,hpmcounter11h
-[ 	]+dc:[ 	]+c8c02573[ 	]+csrr[ 	]+a0,hpmcounter12h
-[ 	]+e0:[ 	]+c8d02573[ 	]+csrr[ 	]+a0,hpmcounter13h
-[ 	]+e4:[ 	]+c8e02573[ 	]+csrr[ 	]+a0,hpmcounter14h
-[ 	]+e8:[ 	]+c8f02573[ 	]+csrr[ 	]+a0,hpmcounter15h
-[ 	]+ec:[ 	]+c9002573[ 	]+csrr[ 	]+a0,hpmcounter16h
-[ 	]+f0:[ 	]+c9102573[ 	]+csrr[ 	]+a0,hpmcounter17h
-[ 	]+f4:[ 	]+c9202573[ 	]+csrr[ 	]+a0,hpmcounter18h
-[ 	]+f8:[ 	]+c9302573[ 	]+csrr[ 	]+a0,hpmcounter19h
-[ 	]+fc:[ 	]+c9402573[ 	]+csrr[ 	]+a0,hpmcounter20h
-[ 	]+100:[ 	]+c9502573[ 	]+csrr[ 	]+a0,hpmcounter21h
-[ 	]+104:[ 	]+c9602573[ 	]+csrr[ 	]+a0,hpmcounter22h
-[ 	]+108:[ 	]+c9702573[ 	]+csrr[ 	]+a0,hpmcounter23h
-[ 	]+10c:[ 	]+c9802573[ 	]+csrr[ 	]+a0,hpmcounter24h
-[ 	]+110:[ 	]+c9902573[ 	]+csrr[ 	]+a0,hpmcounter25h
-[ 	]+114:[ 	]+c9a02573[ 	]+csrr[ 	]+a0,hpmcounter26h
-[ 	]+118:[ 	]+c9b02573[ 	]+csrr[ 	]+a0,hpmcounter27h
-[ 	]+11c:[ 	]+c9c02573[ 	]+csrr[ 	]+a0,hpmcounter28h
-[ 	]+120:[ 	]+c9d02573[ 	]+csrr[ 	]+a0,hpmcounter29h
-[ 	]+124:[ 	]+c9e02573[ 	]+csrr[ 	]+a0,hpmcounter30h
-[ 	]+128:[ 	]+c9f02573[ 	]+csrr[ 	]+a0,hpmcounter31h
-[ 	]+12c:[ 	]+10002573[ 	]+csrr[ 	]+a0,sstatus
-[ 	]+130:[ 	]+10202573[ 	]+csrr[ 	]+a0,sedeleg
-[ 	]+134:[ 	]+10302573[ 	]+csrr[ 	]+a0,sideleg
-[ 	]+138:[ 	]+10402573[ 	]+csrr[ 	]+a0,sie
-[ 	]+13c:[ 	]+10502573[ 	]+csrr[ 	]+a0,stvec
-[ 	]+140:[ 	]+14002573[ 	]+csrr[ 	]+a0,sscratch
-[ 	]+144:[ 	]+14102573[ 	]+csrr[ 	]+a0,sepc
-[ 	]+148:[ 	]+14202573[ 	]+csrr[ 	]+a0,scause
-[ 	]+14c:[ 	]+14302573[ 	]+csrr[ 	]+a0,stval
-[ 	]+150:[ 	]+14402573[ 	]+csrr[ 	]+a0,sip
-[ 	]+154:[ 	]+18002573[ 	]+csrr[ 	]+a0,satp
-[ 	]+158:[ 	]+20002573[ 	]+csrr[ 	]+a0,hstatus
-[ 	]+15c:[ 	]+20202573[ 	]+csrr[ 	]+a0,hedeleg
-[ 	]+160:[ 	]+20302573[ 	]+csrr[ 	]+a0,hideleg
-[ 	]+164:[ 	]+20402573[ 	]+csrr[ 	]+a0,hie
-[ 	]+168:[ 	]+20502573[ 	]+csrr[ 	]+a0,htvec
-[ 	]+16c:[ 	]+24002573[ 	]+csrr[ 	]+a0,hscratch
-[ 	]+170:[ 	]+24102573[ 	]+csrr[ 	]+a0,hepc
-[ 	]+174:[ 	]+24202573[ 	]+csrr[ 	]+a0,hcause
-[ 	]+178:[ 	]+24302573[ 	]+csrr[ 	]+a0,hbadaddr
-[ 	]+17c:[ 	]+24402573[ 	]+csrr[ 	]+a0,hip
-[ 	]+180:[ 	]+f1102573[ 	]+csrr[ 	]+a0,mvendorid
-[ 	]+184:[ 	]+f1202573[ 	]+csrr[ 	]+a0,marchid
-[ 	]+188:[ 	]+f1302573[ 	]+csrr[ 	]+a0,mimpid
-[ 	]+18c:[ 	]+f1402573[ 	]+csrr[ 	]+a0,mhartid
-[ 	]+190:[ 	]+30002573[ 	]+csrr[ 	]+a0,mstatus
-[ 	]+194:[ 	]+30102573[ 	]+csrr[ 	]+a0,misa
-[ 	]+198:[ 	]+30202573[ 	]+csrr[ 	]+a0,medeleg
-[ 	]+19c:[ 	]+30302573[ 	]+csrr[ 	]+a0,mideleg
-[ 	]+1a0:[ 	]+30402573[ 	]+csrr[ 	]+a0,mie
-[ 	]+1a4:[ 	]+30502573[ 	]+csrr[ 	]+a0,mtvec
-[ 	]+1a8:[ 	]+34002573[ 	]+csrr[ 	]+a0,mscratch
-[ 	]+1ac:[ 	]+34102573[ 	]+csrr[ 	]+a0,mepc
-[ 	]+1b0:[ 	]+34202573[ 	]+csrr[ 	]+a0,mcause
-[ 	]+1b4:[ 	]+34302573[ 	]+csrr[ 	]+a0,mtval
-[ 	]+1b8:[ 	]+34402573[ 	]+csrr[ 	]+a0,mip
-[ 	]+1bc:[ 	]+38002573[ 	]+csrr[ 	]+a0,mbase
-[ 	]+1c0:[ 	]+38102573[ 	]+csrr[ 	]+a0,mbound
-[ 	]+1c4:[ 	]+38202573[ 	]+csrr[ 	]+a0,mibase
-[ 	]+1c8:[ 	]+38302573[ 	]+csrr[ 	]+a0,mibound
-[ 	]+1cc:[ 	]+38402573[ 	]+csrr[ 	]+a0,mdbase
-[ 	]+1d0:[ 	]+38502573[ 	]+csrr[ 	]+a0,mdbound
-[ 	]+1d4:[ 	]+b0002573[ 	]+csrr[ 	]+a0,mcycle
-[ 	]+1d8:[ 	]+b0202573[ 	]+csrr[ 	]+a0,minstret
-[ 	]+1dc:[ 	]+b0302573[ 	]+csrr[ 	]+a0,mhpmcounter3
-[ 	]+1e0:[ 	]+b0402573[ 	]+csrr[ 	]+a0,mhpmcounter4
-[ 	]+1e4:[ 	]+b0502573[ 	]+csrr[ 	]+a0,mhpmcounter5
-[ 	]+1e8:[ 	]+b0602573[ 	]+csrr[ 	]+a0,mhpmcounter6
-[ 	]+1ec:[ 	]+b0702573[ 	]+csrr[ 	]+a0,mhpmcounter7
-[ 	]+1f0:[ 	]+b0802573[ 	]+csrr[ 	]+a0,mhpmcounter8
-[ 	]+1f4:[ 	]+b0902573[ 	]+csrr[ 	]+a0,mhpmcounter9
-[ 	]+1f8:[ 	]+b0a02573[ 	]+csrr[ 	]+a0,mhpmcounter10
-[ 	]+1fc:[ 	]+b0b02573[ 	]+csrr[ 	]+a0,mhpmcounter11
-[ 	]+200:[ 	]+b0c02573[ 	]+csrr[ 	]+a0,mhpmcounter12
-[ 	]+204:[ 	]+b0d02573[ 	]+csrr[ 	]+a0,mhpmcounter13
-[ 	]+208:[ 	]+b0e02573[ 	]+csrr[ 	]+a0,mhpmcounter14
-[ 	]+20c:[ 	]+b0f02573[ 	]+csrr[ 	]+a0,mhpmcounter15
-[ 	]+210:[ 	]+b1002573[ 	]+csrr[ 	]+a0,mhpmcounter16
-[ 	]+214:[ 	]+b1102573[ 	]+csrr[ 	]+a0,mhpmcounter17
-[ 	]+218:[ 	]+b1202573[ 	]+csrr[ 	]+a0,mhpmcounter18
-[ 	]+21c:[ 	]+b1302573[ 	]+csrr[ 	]+a0,mhpmcounter19
-[ 	]+220:[ 	]+b1402573[ 	]+csrr[ 	]+a0,mhpmcounter20
-[ 	]+224:[ 	]+b1502573[ 	]+csrr[ 	]+a0,mhpmcounter21
-[ 	]+228:[ 	]+b1602573[ 	]+csrr[ 	]+a0,mhpmcounter22
-[ 	]+22c:[ 	]+b1702573[ 	]+csrr[ 	]+a0,mhpmcounter23
-[ 	]+230:[ 	]+b1802573[ 	]+csrr[ 	]+a0,mhpmcounter24
-[ 	]+234:[ 	]+b1902573[ 	]+csrr[ 	]+a0,mhpmcounter25
-[ 	]+238:[ 	]+b1a02573[ 	]+csrr[ 	]+a0,mhpmcounter26
-[ 	]+23c:[ 	]+b1b02573[ 	]+csrr[ 	]+a0,mhpmcounter27
-[ 	]+240:[ 	]+b1c02573[ 	]+csrr[ 	]+a0,mhpmcounter28
-[ 	]+244:[ 	]+b1d02573[ 	]+csrr[ 	]+a0,mhpmcounter29
-[ 	]+248:[ 	]+b1e02573[ 	]+csrr[ 	]+a0,mhpmcounter30
-[ 	]+24c:[ 	]+b1f02573[ 	]+csrr[ 	]+a0,mhpmcounter31
-[ 	]+250:[ 	]+b8002573[ 	]+csrr[ 	]+a0,mcycleh
-[ 	]+254:[ 	]+b8202573[ 	]+csrr[ 	]+a0,minstreth
-[ 	]+258:[ 	]+b8302573[ 	]+csrr[ 	]+a0,mhpmcounter3h
-[ 	]+25c:[ 	]+b8402573[ 	]+csrr[ 	]+a0,mhpmcounter4h
-[ 	]+260:[ 	]+b8502573[ 	]+csrr[ 	]+a0,mhpmcounter5h
-[ 	]+264:[ 	]+b8602573[ 	]+csrr[ 	]+a0,mhpmcounter6h
-[ 	]+268:[ 	]+b8702573[ 	]+csrr[ 	]+a0,mhpmcounter7h
-[ 	]+26c:[ 	]+b8802573[ 	]+csrr[ 	]+a0,mhpmcounter8h
-[ 	]+270:[ 	]+b8902573[ 	]+csrr[ 	]+a0,mhpmcounter9h
-[ 	]+274:[ 	]+b8a02573[ 	]+csrr[ 	]+a0,mhpmcounter10h
-[ 	]+278:[ 	]+b8b02573[ 	]+csrr[ 	]+a0,mhpmcounter11h
-[ 	]+27c:[ 	]+b8c02573[ 	]+csrr[ 	]+a0,mhpmcounter12h
-[ 	]+280:[ 	]+b8d02573[ 	]+csrr[ 	]+a0,mhpmcounter13h
-[ 	]+284:[ 	]+b8e02573[ 	]+csrr[ 	]+a0,mhpmcounter14h
-[ 	]+288:[ 	]+b8f02573[ 	]+csrr[ 	]+a0,mhpmcounter15h
-[ 	]+28c:[ 	]+b9002573[ 	]+csrr[ 	]+a0,mhpmcounter16h
-[ 	]+290:[ 	]+b9102573[ 	]+csrr[ 	]+a0,mhpmcounter17h
-[ 	]+294:[ 	]+b9202573[ 	]+csrr[ 	]+a0,mhpmcounter18h
-[ 	]+298:[ 	]+b9302573[ 	]+csrr[ 	]+a0,mhpmcounter19h
-[ 	]+29c:[ 	]+b9402573[ 	]+csrr[ 	]+a0,mhpmcounter20h
-[ 	]+2a0:[ 	]+b9502573[ 	]+csrr[ 	]+a0,mhpmcounter21h
-[ 	]+2a4:[ 	]+b9602573[ 	]+csrr[ 	]+a0,mhpmcounter22h
-[ 	]+2a8:[ 	]+b9702573[ 	]+csrr[ 	]+a0,mhpmcounter23h
-[ 	]+2ac:[ 	]+b9802573[ 	]+csrr[ 	]+a0,mhpmcounter24h
-[ 	]+2b0:[ 	]+b9902573[ 	]+csrr[ 	]+a0,mhpmcounter25h
-[ 	]+2b4:[ 	]+b9a02573[ 	]+csrr[ 	]+a0,mhpmcounter26h
-[ 	]+2b8:[ 	]+b9b02573[ 	]+csrr[ 	]+a0,mhpmcounter27h
-[ 	]+2bc:[ 	]+b9c02573[ 	]+csrr[ 	]+a0,mhpmcounter28h
-[ 	]+2c0:[ 	]+b9d02573[ 	]+csrr[ 	]+a0,mhpmcounter29h
-[ 	]+2c4:[ 	]+b9e02573[ 	]+csrr[ 	]+a0,mhpmcounter30h
-[ 	]+2c8:[ 	]+b9f02573[ 	]+csrr[ 	]+a0,mhpmcounter31h
-[ 	]+2cc:[ 	]+32002573[ 	]+csrr[ 	]+a0,mucounteren
-[ 	]+2d0:[ 	]+32102573[ 	]+csrr[ 	]+a0,mscounteren
-[ 	]+2d4:[ 	]+32202573[ 	]+csrr[ 	]+a0,mhcounteren
-[ 	]+2d8:[ 	]+32302573[ 	]+csrr[ 	]+a0,mhpmevent3
-[ 	]+2dc:[ 	]+32402573[ 	]+csrr[ 	]+a0,mhpmevent4
-[ 	]+2e0:[ 	]+32502573[ 	]+csrr[ 	]+a0,mhpmevent5
-[ 	]+2e4:[ 	]+32602573[ 	]+csrr[ 	]+a0,mhpmevent6
-[ 	]+2e8:[ 	]+32702573[ 	]+csrr[ 	]+a0,mhpmevent7
-[ 	]+2ec:[ 	]+32802573[ 	]+csrr[ 	]+a0,mhpmevent8
-[ 	]+2f0:[ 	]+32902573[ 	]+csrr[ 	]+a0,mhpmevent9
-[ 	]+2f4:[ 	]+32a02573[ 	]+csrr[ 	]+a0,mhpmevent10
-[ 	]+2f8:[ 	]+32b02573[ 	]+csrr[ 	]+a0,mhpmevent11
-[ 	]+2fc:[ 	]+32c02573[ 	]+csrr[ 	]+a0,mhpmevent12
-[ 	]+300:[ 	]+32d02573[ 	]+csrr[ 	]+a0,mhpmevent13
-[ 	]+304:[ 	]+32e02573[ 	]+csrr[ 	]+a0,mhpmevent14
-[ 	]+308:[ 	]+32f02573[ 	]+csrr[ 	]+a0,mhpmevent15
-[ 	]+30c:[ 	]+33002573[ 	]+csrr[ 	]+a0,mhpmevent16
-[ 	]+310:[ 	]+33102573[ 	]+csrr[ 	]+a0,mhpmevent17
-[ 	]+314:[ 	]+33202573[ 	]+csrr[ 	]+a0,mhpmevent18
-[ 	]+318:[ 	]+33302573[ 	]+csrr[ 	]+a0,mhpmevent19
-[ 	]+31c:[ 	]+33402573[ 	]+csrr[ 	]+a0,mhpmevent20
-[ 	]+320:[ 	]+33502573[ 	]+csrr[ 	]+a0,mhpmevent21
-[ 	]+324:[ 	]+33602573[ 	]+csrr[ 	]+a0,mhpmevent22
-[ 	]+328:[ 	]+33702573[ 	]+csrr[ 	]+a0,mhpmevent23
-[ 	]+32c:[ 	]+33802573[ 	]+csrr[ 	]+a0,mhpmevent24
-[ 	]+330:[ 	]+33902573[ 	]+csrr[ 	]+a0,mhpmevent25
-[ 	]+334:[ 	]+33a02573[ 	]+csrr[ 	]+a0,mhpmevent26
-[ 	]+338:[ 	]+33b02573[ 	]+csrr[ 	]+a0,mhpmevent27
-[ 	]+33c:[ 	]+33c02573[ 	]+csrr[ 	]+a0,mhpmevent28
-[ 	]+340:[ 	]+33d02573[ 	]+csrr[ 	]+a0,mhpmevent29
-[ 	]+344:[ 	]+33e02573[ 	]+csrr[ 	]+a0,mhpmevent30
-[ 	]+348:[ 	]+33f02573[ 	]+csrr[ 	]+a0,mhpmevent31
-[ 	]+34c:[ 	]+7a002573[ 	]+csrr[ 	]+a0,tselect
-[ 	]+350:[ 	]+7a102573[ 	]+csrr[ 	]+a0,tdata1
-[ 	]+354:[ 	]+7a202573[ 	]+csrr[ 	]+a0,tdata2
-[ 	]+358:[ 	]+7a302573[ 	]+csrr[ 	]+a0,tdata3
-[ 	]+35c:[ 	]+7b002573[ 	]+csrr[ 	]+a0,dcsr
-[ 	]+360:[ 	]+7b102573[ 	]+csrr[ 	]+a0,dpc
-[ 	]+364:[ 	]+7b202573[ 	]+csrr[ 	]+a0,dscratch
-[ 	]+368:[ 	]+04302573[ 	]+csrr[ 	]+a0,utval
-[ 	]+36c:[ 	]+10602573[ 	]+csrr[ 	]+a0,scounteren
-[ 	]+370:[ 	]+14302573[ 	]+csrr[ 	]+a0,stval
-[ 	]+374:[ 	]+18002573[ 	]+csrr[ 	]+a0,satp
-[ 	]+378:[ 	]+30602573[ 	]+csrr[ 	]+a0,mcounteren
-[ 	]+37c:[ 	]+34302573[ 	]+csrr[ 	]+a0,mtval
-[ 	]+380:[ 	]+3a002573[ 	]+csrr[ 	]+a0,pmpcfg0
-[ 	]+384:[ 	]+3a102573[ 	]+csrr[ 	]+a0,pmpcfg1
-[ 	]+388:[ 	]+3a202573[ 	]+csrr[ 	]+a0,pmpcfg2
-[ 	]+38c:[ 	]+3a302573[ 	]+csrr[ 	]+a0,pmpcfg3
-[ 	]+390:[ 	]+3b002573[ 	]+csrr[ 	]+a0,pmpaddr0
-[ 	]+394:[ 	]+3b102573[ 	]+csrr[ 	]+a0,pmpaddr1
-[ 	]+398:[ 	]+3b202573[ 	]+csrr[ 	]+a0,pmpaddr2
-[ 	]+39c:[ 	]+3b302573[ 	]+csrr[ 	]+a0,pmpaddr3
-[ 	]+3a0:[ 	]+3b402573[ 	]+csrr[ 	]+a0,pmpaddr4
-[ 	]+3a4:[ 	]+3b502573[ 	]+csrr[ 	]+a0,pmpaddr5
-[ 	]+3a8:[ 	]+3b602573[ 	]+csrr[ 	]+a0,pmpaddr6
-[ 	]+3ac:[ 	]+3b702573[ 	]+csrr[ 	]+a0,pmpaddr7
-[ 	]+3b0:[ 	]+3b802573[ 	]+csrr[ 	]+a0,pmpaddr8
-[ 	]+3b4:[ 	]+3b902573[ 	]+csrr[ 	]+a0,pmpaddr9
-[ 	]+3b8:[ 	]+3ba02573[ 	]+csrr[ 	]+a0,pmpaddr10
-[ 	]+3bc:[ 	]+3bb02573[ 	]+csrr[ 	]+a0,pmpaddr11
-[ 	]+3c0:[ 	]+3bc02573[ 	]+csrr[ 	]+a0,pmpaddr12
-[ 	]+3c4:[ 	]+3bd02573[ 	]+csrr[ 	]+a0,pmpaddr13
-[ 	]+3c8:[ 	]+3be02573[ 	]+csrr[ 	]+a0,pmpaddr14
-[ 	]+3cc:[ 	]+3bf02573[ 	]+csrr[ 	]+a0,pmpaddr15
diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
deleted file mode 100644
index 72d97f9..0000000
--- a/gas/testsuite/gas/riscv/priv-reg.s
+++ /dev/null
@@ -1,269 +0,0 @@ 
-	.macro csr val
-	csrr a0,\val
-	.endm
-# 1.9.1 registers
-	csr ustatus
-	csr uie
-	csr utvec
-
-	csr uscratch
-	csr uepc
-	csr ucause
-	csr ubadaddr
-	csr uip
-
-	csr fflags
-	csr frm
-	csr fcsr
-
-	csr cycle
-	csr time
-	csr instret
-	csr hpmcounter3
-	csr hpmcounter4
-	csr hpmcounter5
-	csr hpmcounter6
-	csr hpmcounter7
-	csr hpmcounter8
-	csr hpmcounter9
-	csr hpmcounter10
-	csr hpmcounter11
-	csr hpmcounter12
-	csr hpmcounter13
-	csr hpmcounter14
-	csr hpmcounter15
-	csr hpmcounter16
-	csr hpmcounter17
-	csr hpmcounter18
-	csr hpmcounter19
-	csr hpmcounter20
-	csr hpmcounter21
-	csr hpmcounter22
-	csr hpmcounter23
-	csr hpmcounter24
-	csr hpmcounter25
-	csr hpmcounter26
-	csr hpmcounter27
-	csr hpmcounter28
-	csr hpmcounter29
-	csr hpmcounter30
-	csr hpmcounter31
-	csr cycleh
-	csr timeh
-	csr instreth
-	csr hpmcounter3h
-	csr hpmcounter4h
-	csr hpmcounter5h
-	csr hpmcounter6h
-	csr hpmcounter7h
-	csr hpmcounter8h
-	csr hpmcounter9h
-	csr hpmcounter10h
-	csr hpmcounter11h
-	csr hpmcounter12h
-	csr hpmcounter13h
-	csr hpmcounter14h
-	csr hpmcounter15h
-	csr hpmcounter16h
-	csr hpmcounter17h
-	csr hpmcounter18h
-	csr hpmcounter19h
-	csr hpmcounter20h
-	csr hpmcounter21h
-	csr hpmcounter22h
-	csr hpmcounter23h
-	csr hpmcounter24h
-	csr hpmcounter25h
-	csr hpmcounter26h
-	csr hpmcounter27h
-	csr hpmcounter28h
-	csr hpmcounter29h
-	csr hpmcounter30h
-	csr hpmcounter31h
-
-	csr sstatus
-	csr sedeleg
-	csr sideleg
-	csr sie
-	csr stvec
-
-	csr sscratch
-	csr sepc
-	csr scause
-	csr sbadaddr
-	csr sip
-
-	csr sptbr
-
-	csr hstatus
-	csr hedeleg
-	csr hideleg
-	csr hie
-	csr htvec
-
-	csr hscratch
-	csr hepc
-	csr hcause
-	csr hbadaddr
-	csr hip
-
-	csr mvendorid
-	csr marchid
-	csr mimpid
-	csr mhartid
-
-	csr mstatus
-	csr misa
-	csr medeleg
-	csr mideleg
-	csr mie
-	csr mtvec
-
-	csr mscratch
-	csr mepc
-	csr mcause
-	csr mbadaddr
-	csr mip
-
-	csr mbase
-	csr mbound
-	csr mibase
-	csr mibound
-	csr mdbase
-	csr mdbound
-
-	csr mcycle
-	csr minstret
-	csr mhpmcounter3
-	csr mhpmcounter4
-	csr mhpmcounter5
-	csr mhpmcounter6
-	csr mhpmcounter7
-	csr mhpmcounter8
-	csr mhpmcounter9
-	csr mhpmcounter10
-	csr mhpmcounter11
-	csr mhpmcounter12
-	csr mhpmcounter13
-	csr mhpmcounter14
-	csr mhpmcounter15
-	csr mhpmcounter16
-	csr mhpmcounter17
-	csr mhpmcounter18
-	csr mhpmcounter19
-	csr mhpmcounter20
-	csr mhpmcounter21
-	csr mhpmcounter22
-	csr mhpmcounter23
-	csr mhpmcounter24
-	csr mhpmcounter25
-	csr mhpmcounter26
-	csr mhpmcounter27
-	csr mhpmcounter28
-	csr mhpmcounter29
-	csr mhpmcounter30
-	csr mhpmcounter31
-	csr mcycleh
-	csr minstreth
-	csr mhpmcounter3h
-	csr mhpmcounter4h
-	csr mhpmcounter5h
-	csr mhpmcounter6h
-	csr mhpmcounter7h
-	csr mhpmcounter8h
-	csr mhpmcounter9h
-	csr mhpmcounter10h
-	csr mhpmcounter11h
-	csr mhpmcounter12h
-	csr mhpmcounter13h
-	csr mhpmcounter14h
-	csr mhpmcounter15h
-	csr mhpmcounter16h
-	csr mhpmcounter17h
-	csr mhpmcounter18h
-	csr mhpmcounter19h
-	csr mhpmcounter20h
-	csr mhpmcounter21h
-	csr mhpmcounter22h
-	csr mhpmcounter23h
-	csr mhpmcounter24h
-	csr mhpmcounter25h
-	csr mhpmcounter26h
-	csr mhpmcounter27h
-	csr mhpmcounter28h
-	csr mhpmcounter29h
-	csr mhpmcounter30h
-	csr mhpmcounter31h
-
-	csr mucounteren
-	csr mscounteren
-	csr mhcounteren
-
-	csr mhpmevent3
-	csr mhpmevent4
-	csr mhpmevent5
-	csr mhpmevent6
-	csr mhpmevent7
-	csr mhpmevent8
-	csr mhpmevent9
-	csr mhpmevent10
-	csr mhpmevent11
-	csr mhpmevent12
-	csr mhpmevent13
-	csr mhpmevent14
-	csr mhpmevent15
-	csr mhpmevent16
-	csr mhpmevent17
-	csr mhpmevent18
-	csr mhpmevent19
-	csr mhpmevent20
-	csr mhpmevent21
-	csr mhpmevent22
-	csr mhpmevent23
-	csr mhpmevent24
-	csr mhpmevent25
-	csr mhpmevent26
-	csr mhpmevent27
-	csr mhpmevent28
-	csr mhpmevent29
-	csr mhpmevent30
-	csr mhpmevent31
-
-	csr tselect
-	csr tdata1
-	csr tdata2
-	csr tdata3
-
-	csr dcsr
-	csr dpc
-	csr dscratch
-# 1.10 registers
-	csr utval
-
-	csr scounteren
-	csr stval
-	csr satp
-
-	csr mcounteren
-	csr mtval
-
-	csr pmpcfg0
-	csr pmpcfg1
-	csr pmpcfg2
-	csr pmpcfg3
-	csr pmpaddr0
-	csr pmpaddr1
-	csr pmpaddr2
-	csr pmpaddr3
-	csr pmpaddr4
-	csr pmpaddr5
-	csr pmpaddr6
-	csr pmpaddr7
-	csr pmpaddr8
-	csr pmpaddr9
-	csr pmpaddr10
-	csr pmpaddr11
-	csr pmpaddr12
-	csr pmpaddr13
-	csr pmpaddr14
-	csr pmpaddr15
diff --git a/gas/testsuite/gas/riscv/satp.d b/gas/testsuite/gas/riscv/satp.d
deleted file mode 100644
index 823601c..0000000
--- a/gas/testsuite/gas/riscv/satp.d
+++ /dev/null
@@ -1,11 +0,0 @@ 
-#as:
-#objdump: -dr
-
-.*:[ 	]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ 	]+0:[ 	]+180022f3[ 	]+csrr[ 	]+t0,satp
-[ 	]+4:[ 	]+180022f3[ 	]+csrr[ 	]+t0,satp
diff --git a/gas/testsuite/gas/riscv/satp.s b/gas/testsuite/gas/riscv/satp.s
deleted file mode 100644
index f8aa766..0000000
--- a/gas/testsuite/gas/riscv/satp.s
+++ /dev/null
@@ -1,3 +0,0 @@ 
-target:
-	csrr t0, satp
-	csrr t0, sptbr
diff --git a/gdb/features/riscv/32bit-csr.xml b/gdb/features/riscv/32bit-csr.xml
index da1bf19..a9ea54d 100644
--- a/gdb/features/riscv/32bit-csr.xml
+++ b/gdb/features/riscv/32bit-csr.xml
@@ -227,24 +227,32 @@ 
   <reg name="tdata3" bitsize="32"/>
   <reg name="dcsr" bitsize="32"/>
   <reg name="dpc" bitsize="32"/>
-  <reg name="dscratch" bitsize="32"/>
   <reg name="hstatus" bitsize="32"/>
   <reg name="hedeleg" bitsize="32"/>
   <reg name="hideleg" bitsize="32"/>
-  <reg name="hie" bitsize="32"/>
-  <reg name="htvec" bitsize="32"/>
-  <reg name="hscratch" bitsize="32"/>
-  <reg name="hepc" bitsize="32"/>
-  <reg name="hcause" bitsize="32"/>
-  <reg name="hbadaddr" bitsize="32"/>
-  <reg name="hip" bitsize="32"/>
+  <reg name="hcounteren" bitsize="32"/>
+  <reg name="hgatp" bitsize="32"/>
+  <reg name="htimedelta" bitsize="32"/>
+  <reg name="htimedeltah" bitsize="32"/>
+  <reg name="vsstatus" bitsize="32"/>
+  <reg name="vsie" bitsize="32"/>
+  <reg name="vstvec" bitsize="32"/>
+  <reg name="vsscratch" bitsize="32"/>
+  <reg name="vsepc" bitsize="32"/>
+  <reg name="vscause" bitsize="32"/>
+  <reg name="vstval" bitsize="32"/>
+  <reg name="vsip" bitsize="32"/>
+  <reg name="vsatp" bitsize="32"/>
+  <reg name="mstatush" bitsize="32"/>
+  <reg name="mcountinhibit" bitsize="32"/>
+  <reg name="dscratch0" bitsize="32"/>
+  <reg name="dscratch1" bitsize="32"/>
   <reg name="mbase" bitsize="32"/>
   <reg name="mbound" bitsize="32"/>
   <reg name="mibase" bitsize="32"/>
   <reg name="mibound" bitsize="32"/>
   <reg name="mdbase" bitsize="32"/>
   <reg name="mdbound" bitsize="32"/>
-  <reg name="mucounteren" bitsize="32"/>
   <reg name="mscounteren" bitsize="32"/>
   <reg name="mhcounteren" bitsize="32"/>
 </feature>
diff --git a/gdb/features/riscv/64bit-csr.xml b/gdb/features/riscv/64bit-csr.xml
index 6aa4bed..b32b413 100644
--- a/gdb/features/riscv/64bit-csr.xml
+++ b/gdb/features/riscv/64bit-csr.xml
@@ -227,24 +227,32 @@ 
   <reg name="tdata3" bitsize="64"/>
   <reg name="dcsr" bitsize="64"/>
   <reg name="dpc" bitsize="64"/>
-  <reg name="dscratch" bitsize="64"/>
   <reg name="hstatus" bitsize="64"/>
   <reg name="hedeleg" bitsize="64"/>
   <reg name="hideleg" bitsize="64"/>
-  <reg name="hie" bitsize="64"/>
-  <reg name="htvec" bitsize="64"/>
-  <reg name="hscratch" bitsize="64"/>
-  <reg name="hepc" bitsize="64"/>
-  <reg name="hcause" bitsize="64"/>
-  <reg name="hbadaddr" bitsize="64"/>
-  <reg name="hip" bitsize="64"/>
+  <reg name="hcounteren" bitsize="64"/>
+  <reg name="hgatp" bitsize="64"/>
+  <reg name="htimedelta" bitsize="64"/>
+  <reg name="htimedeltah" bitsize="64"/>
+  <reg name="vsstatus" bitsize="64"/>
+  <reg name="vsie" bitsize="64"/>
+  <reg name="vstvec" bitsize="64"/>
+  <reg name="vsscratch" bitsize="64"/>
+  <reg name="vsepc" bitsize="64"/>
+  <reg name="vscause" bitsize="64"/>
+  <reg name="vstval" bitsize="64"/>
+  <reg name="vsip" bitsize="64"/>
+  <reg name="vsatp" bitsize="64"/>
+  <reg name="mstatush" bitsize="64"/>
+  <reg name="mcountinhibit" bitsize="64"/>
+  <reg name="dscratch0" bitsize="64"/>
+  <reg name="dscratch1" bitsize="64"/>
   <reg name="mbase" bitsize="64"/>
   <reg name="mbound" bitsize="64"/>
   <reg name="mibase" bitsize="64"/>
   <reg name="mibound" bitsize="64"/>
   <reg name="mdbase" bitsize="64"/>
   <reg name="mdbound" bitsize="64"/>
-  <reg name="mucounteren" bitsize="64"/>
   <reg name="mscounteren" bitsize="64"/>
   <reg name="mhcounteren" bitsize="64"/>
 </feature>
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index f09200c..ee3d976 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -795,18 +795,31 @@ 
 #define CSR_TDATA3 0x7a3
 #define CSR_DCSR 0x7b0
 #define CSR_DPC 0x7b1
-#define CSR_DSCRATCH 0x7b2
+/* These registers are present in priv spec 1.12.  */
+#define CSR_HSTATUS 0x600
+#define CSR_HEDELEG 0x602
+#define CSR_HIDELEG 0x603
+#define CSR_HCOUNTEREN 0x606
+#define CSR_HGATP 0x680
+#define CSR_HTIMEDELTA 0x605
+#define CSR_HTIMEDELTAH 0x615
+#define CSR_VSSTATUS 0x200
+#define CSR_VSIE 0x204
+#define CSR_VSTVEC 0x205
+#define CSR_VSSCRATCH 0x240
+#define CSR_VSEPC 0x241
+#define CSR_VSCAUSE 0x242
+#define CSR_VSTVAL 0x243
+#define CSR_VSIP 0x244
+#define CSR_VSATP 0x280
+#define CSR_MSTATUSH 0x310
+#define CSR_MCOUNTINHIBIT 0x320
+#define CSR_DSCRATCH0 0x7b2
+#define CSR_DSCRATCH1 0x7b3
 /* These registers are present in priv spec 1.9.1, dropped in 1.10.  */
-#define CSR_HSTATUS 0x200
-#define CSR_HEDELEG 0x202
-#define CSR_HIDELEG 0x203
-#define CSR_HIE 0x204
-#define CSR_HTVEC 0x205
-#define CSR_HSCRATCH 0x240
-#define CSR_HEPC 0x241
-#define CSR_HCAUSE 0x242
-#define CSR_HBADADDR 0x243
-#define CSR_HIP 0x244
+/* CSR_HSTATUS is 0x200 in 1.9.1, dropped in 1.10, but 0x600 in 1.12.  */
+/* CSR_HEDELEG is 0x202 in 1.9.1, dropped in 1.10, but 0x602 in 1.12.  */
+/* CSR_HIDELEG is 0x203 in 1.9.1, dropped in 1.10, but 0x603 in 1.12.  */
 /* CSR_MISA is 0xf10 in 1.9, but 0x301 in 1.9.1.  */
 #define CSR_MBASE 0x380
 #define CSR_MBOUND 0x381
@@ -814,7 +827,6 @@ 
 #define CSR_MIBOUND 0x383
 #define CSR_MDBASE 0x384
 #define CSR_MDBOUND 0x385
-#define CSR_MUCOUNTEREN 0x320
 #define CSR_MSCOUNTEREN 0x321
 #define CSR_MHCOUNTEREN 0x322
 #define CAUSE_MISALIGNED_FETCH 0x0
@@ -1336,25 +1348,34 @@  DECLARE_CSR(tdata2, CSR_TDATA2)
 DECLARE_CSR(tdata3, CSR_TDATA3)
 DECLARE_CSR(dcsr, CSR_DCSR)
 DECLARE_CSR(dpc, CSR_DPC)
-DECLARE_CSR(dscratch, CSR_DSCRATCH)
-/* These registers are present in priv spec 1.9.1, dropped in 1.10.  */
+/* These registers are present in priv spec 1.12.  */
 DECLARE_CSR(hstatus, CSR_HSTATUS)
 DECLARE_CSR(hedeleg, CSR_HEDELEG)
 DECLARE_CSR(hideleg, CSR_HIDELEG)
-DECLARE_CSR(hie, CSR_HIE)
-DECLARE_CSR(htvec, CSR_HTVEC)
-DECLARE_CSR(hscratch, CSR_HSCRATCH)
-DECLARE_CSR(hepc, CSR_HEPC)
-DECLARE_CSR(hcause, CSR_HCAUSE)
-DECLARE_CSR(hbadaddr, CSR_HBADADDR)
-DECLARE_CSR(hip, CSR_HIP)
+DECLARE_CSR(hcounteren, CSR_HCOUNTEREN)
+DECLARE_CSR(hgatp, CSR_HGATP)
+DECLARE_CSR(htimedelta, CSR_HTIMEDELTA)
+DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH)
+DECLARE_CSR(vsstatus, CSR_VSSTATUS)
+DECLARE_CSR(vsie, CSR_VSIE)
+DECLARE_CSR(vstvec, CSR_VSTVEC)
+DECLARE_CSR(vsscratch, CSR_VSSCRATCH)
+DECLARE_CSR(vsepc, CSR_VSEPC)
+DECLARE_CSR(vscause, CSR_VSCAUSE)
+DECLARE_CSR(vstval, CSR_VSTVAL)
+DECLARE_CSR(vsip, CSR_VSIP)
+DECLARE_CSR(vsatp, CSR_VSATP)
+DECLARE_CSR(mstatush, CSR_MSTATUSH)
+DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT)
+DECLARE_CSR(dscratch0, CSR_DSCRATCH0)
+DECLARE_CSR(dscratch1, CSR_DSCRATCH1)
+/* These registers are present in priv spec 1.9.1, dropped in 1.10.  */
 DECLARE_CSR(mbase, CSR_MBASE)
 DECLARE_CSR(mbound, CSR_MBOUND)
 DECLARE_CSR(mibase, CSR_MIBASE)
 DECLARE_CSR(mibound, CSR_MIBOUND)
 DECLARE_CSR(mdbase, CSR_MDBASE)
 DECLARE_CSR(mdbound, CSR_MDBOUND)
-DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
 DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
 DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN)
 #endif
@@ -1367,6 +1388,24 @@  DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL)
 DECLARE_CSR_ALIAS(sptbr, CSR_SATP)
 /* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10.  */
 DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL)
+/* Hie is 0x204 in 1.9.1, but 0x204 is vsie in 1.12.  */
+DECLARE_CSR_ALIAS(hie, CSR_VSIE)
+/* Htvec is 0x205 in 1.9.1, but 0x205 is vstvec in 1.12.  */
+DECLARE_CSR_ALIAS(htvec, CSR_VSTVEC)
+/* Hscratch is 0x240 in 1.9.1, but 0x240 is vsscratch in 1.12.  */
+DECLARE_CSR_ALIAS(hscratch, CSR_VSSCRATCH)
+/* Hepc is 0x241 in 1.9.1, but 0x241 is vsepc in 1.12.  */
+DECLARE_CSR_ALIAS(hepc, CSR_VSEPC)
+/* Hcause is 0x242 in 1.9.1, but 0x242 is vscause in 1.12.  */
+DECLARE_CSR_ALIAS(hcause, CSR_VSCAUSE)
+/* Hbadaddr is 0x243 in 1.9.1, but 0x243 is vstval in 1.12.  */
+DECLARE_CSR_ALIAS(hbadaddr, CSR_VSTVAL)
+/* Hip is 0x244 in 1.9.1, but 0x244 is vsip in 1.12.  */
+DECLARE_CSR_ALIAS(hip, CSR_VSIP)
+/* Mucounteren is 0x320 in 1.9.1, but 0x320 is mcountinhibit in 1.12.  */
+DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT)
+/* Dscratch is 0x7b2 in 1.10, but 0x7b2 is dscratch0 in 1.12.  */
+DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0)
 #endif
 #ifdef DECLARE_CAUSE
 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)