[v2,4/4] RISC-V: Disable the CSR checking by default.

Message ID 1575358697-17241-5-git-send-email-nelson.chu@sifive.com
State Superseded
Headers show
Series
  • [v2,1/4] RISC-V: Update the CSR to privilege spec 1.12.
Related show

Commit Message

Nelson Chu Dec. 3, 2019, 7:38 a.m.
Add new .option `csrcheck/nocsrcheck` and GAS option `-mcsrcheck/-mno-csrcheck`
to enbale/disable the CSR checking.  Disable the CSR checking by default.

	gas/
	* config/tc-riscv.c: Add new .option and GAS options to enbale/disable
	the CSR checking.  We disable the CSR checking by default.
	(riscv_ip, reg_lookup_internal): Check the `riscv_opts.csrcheck`
	before we doing the CSR checking.
	* doc/c-riscv.texi: Add description for the new .option and assembler
	options.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsrcheck` to enable
	the CSR checking.
	* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
---
 gas/config/tc-riscv.c                              | 23 +++++++++++++++++++++-
 gas/doc/c-riscv.texi                               | 13 ++++++++++++
 gas/testsuite/gas/riscv/priv-reg-fail-fext.d       |  2 +-
 .../gas/riscv/priv-reg-fail-read-only-01.d         |  2 +-
 .../gas/riscv/priv-reg-fail-read-only-02.d         |  2 +-
 gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d  |  2 +-
 6 files changed, 39 insertions(+), 5 deletions(-)

-- 
2.7.4

Patch

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 7ab7de2..3042d69 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -83,6 +83,7 @@  struct riscv_set_options
   int rve; /* Generate RVE code.  */
   int relax; /* Emit relocs the linker is allowed to relax.  */
   int arch_attr; /* Emit arch attribute.  */
+  int csrcheck; /* Enable the CSR checking.  */
 };
 
 static struct riscv_set_options riscv_opts =
@@ -92,6 +93,7 @@  static struct riscv_set_options riscv_opts =
   0,	/* rve */
   1,	/* relax */
   DEFAULT_RISCV_ATTR, /* arch_attr */
+  0.	/* csrcheck */
 };
 
 static void
@@ -566,7 +568,9 @@  reg_lookup_internal (const char *s, enum reg_class class)
   if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
     return -1;
 
-  if (class == RCLASS_CSR && !reg_csr_lookup_internal (s))
+  if (class == RCLASS_CSR
+      && riscv_opts.csrcheck
+      && !reg_csr_lookup_internal (s))
     return -1;
 
   return DECODE_REG_NUM (r);
@@ -1590,6 +1594,7 @@  riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		  /* Check if we write a read-only CSR by the CSR
 		     instruction.  */
 		  if (insn_with_csr
+		      && riscv_opts.csrcheck
 		      && !riscv_csr_read_only_check (ip->insn_opcode))
 		    {
 		      /* Don't parse the next insn in the riscv_opcode.
@@ -2328,6 +2333,8 @@  enum options
   OPTION_NO_RELAX,
   OPTION_ARCH_ATTR,
   OPTION_NO_ARCH_ATTR,
+  OPTION_CSR_CHECK,
+  OPTION_NO_CSR_CHECK,
   OPTION_END_OF_ENUM
 };
 
@@ -2342,6 +2349,8 @@  struct option md_longopts[] =
   {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
   {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
   {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
+  {"mcsrcheck", no_argument, NULL, OPTION_CSR_CHECK},
+  {"mno-csrcheck", no_argument, NULL, OPTION_NO_CSR_CHECK},
 
   {NULL, no_argument, NULL, 0}
 };
@@ -2420,6 +2429,14 @@  md_parse_option (int c, const char *arg)
       riscv_opts.arch_attr = FALSE;
       break;
 
+    case OPTION_CSR_CHECK:
+      riscv_opts.csrcheck = TRUE;
+      break;
+
+    case OPTION_NO_CSR_CHECK:
+      riscv_opts.csrcheck = FALSE;
+      break;
+
     default:
       return 0;
     }
@@ -2812,6 +2829,10 @@  s_riscv_option (int x ATTRIBUTE_UNUSED)
     riscv_opts.relax = TRUE;
   else if (strcmp (name, "norelax") == 0)
     riscv_opts.relax = FALSE;
+  else if (strcmp (name, "csrcheck") == 0)
+    riscv_opts.csrcheck = TRUE;
+  else if (strcmp (name, "nocsrcheck") == 0)
+    riscv_opts.csrcheck = FALSE;
   else if (strcmp (name, "push") == 0)
     {
       struct riscv_option_stack *s;
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 9bc8c82..644e332 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -59,6 +59,15 @@  required to materialize symbol addresses. (default)
 @item -mno-relax
 Don't do linker relaxations.
 
+@cindex @samp{-mcsrcheck} option, RISC-V
+@item -mcsrcheck
+Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
+The ISA-dependent CSR are only valid when the specific ISA is set.  The
+read-only CSR can not be written by the CSR instructions.
+
+@cindex @samp{-mno-csrcheck} option, RISC-V
+@item -mno-csrcheck
+Don't do CSR cheching.
 @end table
 @c man end
 
@@ -160,6 +169,10 @@  opportunistically relax some code sequences, but sometimes this behavior is not
 desirable.
 @end table
 
+@item csrcheck
+@itemx nocsrcheck
+Enables or disables the CSR checking.
+
 @cindex INSN directives
 @item .insn @var{value}
 @itemx .insn @var{value}
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
index 4c27f47..2b9faeb 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
@@ -1,3 +1,3 @@ 
-#as: -march=rv32i
+#as: -march=rv32i -mcsrcheck
 #source: priv-reg-all.s
 #error_output: priv-reg-fail-fext.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
index 9c93d8a..72ff57b 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
@@ -1,3 +1,3 @@ 
-#as: -march=rv32if
+#as: -march=rv32if -mcsrcheck
 #source: priv-reg-fail-read-only-01.s
 #error_output: priv-reg-fail-read-only-01.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
index ede45c5..22ad2da 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
@@ -1,3 +1,3 @@ 
-#as: -march=rv32if
+#as: -march=rv32if -mcsrcheck
 #source: priv-reg-fail-read-only-02.s
 #error_output: priv-reg-fail-read-only-02.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
index 88038bd..e45337f 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
@@ -1,3 +1,3 @@ 
-#as: -march=rv64if
+#as: -march=rv64if -mcsrcheck
 #source: priv-reg-all.s
 #error_output: priv-reg-fail-rv32-only.l