[2/2] Arm64: simplify Crypto arch extension handling

Message ID 80b917a5-3bd2-d3db-a89f-8f795813d222@suse.com
State New
Headers show
Series
  • Arm64: arch extension handling adjustments
Related show

Commit Message

Jan Beulich Nov. 25, 2019, 9:41 a.m.
This, at the assembler level, is just a "brace" feature covering both
AES and SHA2. Hence there's no need for it to have a separate feature
flag, freeing up a bit for future re-use. Along these lines there are
also a number of dead definitions/variables in the opcode table file.

gas/
2019-11-XX  Jan Beulich  <jbeulich@suse.com>

	* config/tc-aarch64.c (aarch64_features): Drop redundant AES and
	SHA2 flags from "crypto" entry.

include/
2019-11-XX  Jan Beulich  <jbeulich@suse.com>

	* opcode/aarch64.h (AARCH64_FEATURE_CRYPTO): Expand to the
	combination of AES and SHA2.

opcodes/
2019-11-XX  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_feature_crypto,
	aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
	CRYPTO_V8_2_INSN): Delete.

Patch

--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8932,9 +8932,7 @@  struct aarch64_option_cpu_value_table
 static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"crc",		AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0),
 			AARCH64_ARCH_NONE},
-  {"crypto",		AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
-					 | AARCH64_FEATURE_AES
-					 | AARCH64_FEATURE_SHA2, 0),
+  {"crypto",		AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0),
 			AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
   {"fp",		AARCH64_FEATURE (AARCH64_FEATURE_FP, 0),
 			AARCH64_ARCH_NONE},
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -45,7 +45,6 @@  typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_V8	0x00000001	/* All processors.  */
 #define AARCH64_FEATURE_V8_2	0x00000020      /* ARMv8.2 processors.  */
 #define AARCH64_FEATURE_V8_3	0x00000040      /* ARMv8.3 processors.  */
-#define AARCH64_FEATURE_CRYPTO	0x00010000	/* Crypto instructions.  */
 #define AARCH64_FEATURE_FP	0x00020000	/* FP instructions.  */
 #define AARCH64_FEATURE_SIMD	0x00040000	/* SIMD instructions.  */
 #define AARCH64_FEATURE_CRC	0x00080000	/* CRC instructions.  */
@@ -96,6 +95,9 @@  typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_SVE2_SM4		0x000000200
 #define AARCH64_FEATURE_SVE2_SHA3	0x000000400
 
+/* Crypto instructions are the combination of AES and SHA2.  */
+#define AARCH64_FEATURE_CRYPTO	(AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
+
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8		AARCH64_FEATURE (AARCH64_FEATURE_V8, \
 						 AARCH64_FEATURE_FP  \
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2266,9 +2266,6 @@  static const aarch64_feature_set aarch64
   AARCH64_FEATURE (AARCH64_FEATURE_FP, 0);
 static const aarch64_feature_set aarch64_feature_simd =
   AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0);
-static const aarch64_feature_set aarch64_feature_crypto =
-  AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO | AARCH64_FEATURE_AES
-		   | AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0);
 static const aarch64_feature_set aarch64_feature_crc =
   AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
 static const aarch64_feature_set aarch64_feature_lse =
@@ -2305,9 +2302,6 @@  static const aarch64_feature_set aarch64
   AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_AES, 0);
 static const aarch64_feature_set aarch64_feature_v8_4 =
   AARCH64_FEATURE (AARCH64_FEATURE_V8_4, 0);
-static const aarch64_feature_set aarch64_feature_crypto_v8_2 =
-  AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_CRYPTO
-		   | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0);
 static const aarch64_feature_set aarch64_feature_sm4 =
   AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_SM4
 		   | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0);
@@ -2348,7 +2342,6 @@  static const aarch64_feature_set aarch64
 #define CORE		&aarch64_feature_v8
 #define FP		&aarch64_feature_fp
 #define SIMD		&aarch64_feature_simd
-#define CRYPTO		&aarch64_feature_crypto
 #define CRC		&aarch64_feature_crc
 #define LSE		&aarch64_feature_lse
 #define LOR		&aarch64_feature_lor
@@ -2368,7 +2361,6 @@  static const aarch64_feature_set aarch64
 #define ARMV8_4		&aarch64_feature_v8_4
 #define SHA3		&aarch64_feature_sha3
 #define SM4		&aarch64_feature_sm4
-#define CRYPTO_V8_2	&aarch64_feature_crypto_v8_2
 #define FP_F16_V8_2	&aarch64_feature_fp_16_v8_2
 #define DOTPROD		&aarch64_feature_dotprod
 #define ARMV8_5		&aarch64_feature_v8_5
@@ -2393,8 +2385,6 @@  static const aarch64_feature_set aarch64
   { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define _SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,VERIFIER) \
   { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, VERIFIER }
-#define CRYP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-  { NAME, OPCODE, MASK, CLASS, 0, CRYPTO, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@@ -2427,8 +2417,6 @@  static const aarch64_feature_set aarch64
   { NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define V8_4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, ARMV8_4, OPS, QUALS, FLAGS, 0, 0, NULL }
-#define CRYPTO_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-  { NAME, OPCODE, MASK, CLASS, 0, CRYPTO_V8_2, OPS, QUALS, FLAGS, 0, NULL }
 #define SHA3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define SM4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \