x86: consolidate tracking of MMX register use

Message ID 8043f4b3-9128-b02a-092f-7b7d742de353@suse.com
State New
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Series
  • x86: consolidate tracking of MMX register use
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Commit Message

Jan Beulich Nov. 25, 2019, 7:33 a.m.
Just like for XMM/YMM/ZMM don't key this to any Cpu* flags. Instead
include the two special insns (not having register operands) explicitly.

gas/
2019-11-XX  Jan Beulich  <jbeulich@suse.com>

	* config/tc-i386.c (output_insn): Don't consider Cpu* settings
	when setting GNU_PROPERTY_X86_FEATURE_2_MMX.

Comments

H.J. Lu Dec. 3, 2019, 5:29 p.m. | #1
On Sun, Nov 24, 2019 at 11:33 PM Jan Beulich <jbeulich@suse.com> wrote:
>

> Just like for XMM/YMM/ZMM don't key this to any Cpu* flags. Instead

> include the two special insns (not having register operands) explicitly.

>

> gas/

> 2019-11-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * config/tc-i386.c (output_insn): Don't consider Cpu* settings

>         when setting GNU_PROPERTY_X86_FEATURE_2_MMX.

>


OK.

Thanks.

-- 
H.J.

Patch

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -8251,15 +8251,9 @@  output_insn (void)
 	  || i.tm.cpu_flags.bitfield.cpu687
 	  || i.tm.cpu_flags.bitfield.cpufisttp)
 	x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
-      /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
-	 Xfence instructions.  */
-      if (i.tm.base_opcode != 0xf18
-	  && i.tm.base_opcode != 0xf0d
-	  && i.tm.base_opcode != 0xfaef8
-	  && (i.has_regmmx
-	      || i.tm.cpu_flags.bitfield.cpummx
-	      || i.tm.cpu_flags.bitfield.cpua3dnow
-	      || i.tm.cpu_flags.bitfield.cpua3dnowa))
+      if (i.has_regmmx
+	  || i.tm.base_opcode == 0xf77 /* emms */
+	  || i.tm.base_opcode == 0xf0e /* femms */)
 	x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
       if (i.has_regxmm)
 	x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;