x86: drop redundant SYSCALL/SYSRET templates

Message ID 34aba8af-9287-beea-03b3-7442134f1a31@suse.com
State New
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  • x86: drop redundant SYSCALL/SYSRET templates
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Commit Message

Jan Beulich Nov. 11, 2019, noon
The Cpu64 forms are no different in their attributes except for the CPU
flags; there's no need to key these off of anything other than
CpuSYSCALL even for the 64-bit forms. Dropping these improves the
diagnostic on SYSRETQ used in 32-bit code from "unsupported instruction
`sysret'" to "invalid instruction suffix for `sysret'".

opcodes/
2019-11-XX  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
	* i386-tbl.h: Re-generate.

Comments

H.J. Lu Nov. 11, 2019, 5:15 p.m. | #1
On Mon, Nov 11, 2019 at 4:01 AM Jan Beulich <jbeulich@suse.com> wrote:
>

> The Cpu64 forms are no different in their attributes except for the CPU

> flags; there's no need to key these off of anything other than

> CpuSYSCALL even for the 64-bit forms. Dropping these improves the

> diagnostic on SYSRETQ used in 32-bit code from "unsupported instruction

> `sysret'" to "invalid instruction suffix for `sysret'".

>

> opcodes/

> 2019-11-XX  Jan Beulich  <jbeulich@suse.com>

>

>         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.

>         * i386-tbl.h: Re-generate.

>

> --- a/opcodes/i386-opc.tbl

> +++ b/opcodes/i386-opc.tbl

> @@ -2797,9 +2797,7 @@ pswapd, 2, 0xf0f, 0xbb, 2, Cpu3dnowA, Mo

>

>  // AMD extensions.

>  syscall, 0, 0xf05, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

> -syscall, 0, 0xf05, None, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

>  sysret, 0, 0xf07, None, 2, CpuSYSCALL, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }

> -sysret, 0, 0xf07, None, 2, Cpu64, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }

>  swapgs, 0, 0xf01f8, None, 3, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

>  rdtscp, 0, 0xf01f9, None, 3, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

>


Can you add a testcase?

Thanks.

-- 
H.J.
Jan Beulich Nov. 12, 2019, 7:20 a.m. | #2
On 11.11.2019 18:15,  H.J. Lu  wrote:
> On Mon, Nov 11, 2019 at 4:01 AM Jan Beulich <jbeulich@suse.com> wrote:

>> --- a/opcodes/i386-opc.tbl

>> +++ b/opcodes/i386-opc.tbl

>> @@ -2797,9 +2797,7 @@ pswapd, 2, 0xf0f, 0xbb, 2, Cpu3dnowA, Mo

>>

>>  // AMD extensions.

>>  syscall, 0, 0xf05, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

>> -syscall, 0, 0xf05, None, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

>>  sysret, 0, 0xf07, None, 2, CpuSYSCALL, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }

>> -sysret, 0, 0xf07, None, 2, Cpu64, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }

>>  swapgs, 0, 0xf01f8, None, 3, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

>>  rdtscp, 0, 0xf01f9, None, 3, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

> 

> Can you add a testcase?


The insns are being tested already, so I wonder what you want to be
tested in addition. What completely lacks testing are SYSENTER/SYSEXIT.

Jan
H.J. Lu Nov. 12, 2019, 8:45 p.m. | #3
On Mon, Nov 11, 2019 at 11:19 PM Jan Beulich <jbeulich@suse.com> wrote:
>

> On 11.11.2019 18:15,  H.J. Lu  wrote:

> > On Mon, Nov 11, 2019 at 4:01 AM Jan Beulich <jbeulich@suse.com> wrote:

> >> --- a/opcodes/i386-opc.tbl

> >> +++ b/opcodes/i386-opc.tbl

> >> @@ -2797,9 +2797,7 @@ pswapd, 2, 0xf0f, 0xbb, 2, Cpu3dnowA, Mo

> >>

> >>  // AMD extensions.

> >>  syscall, 0, 0xf05, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

> >> -syscall, 0, 0xf05, None, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

> >>  sysret, 0, 0xf07, None, 2, CpuSYSCALL, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }

> >> -sysret, 0, 0xf07, None, 2, Cpu64, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }

> >>  swapgs, 0, 0xf01f8, None, 3, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

> >>  rdtscp, 0, 0xf01f9, None, 3, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

> >

> > Can you add a testcase?

>

> The insns are being tested already, so I wonder what you want to be

> tested in addition. What completely lacks testing are SYSENTER/SYSEXIT.

>


That is fine then.

Thanks.

-- 
H.J.
Jan Beulich Nov. 13, 2019, 1:19 p.m. | #4
On 12.11.2019 21:45,  H.J. Lu  wrote:
> On Mon, Nov 11, 2019 at 11:19 PM Jan Beulich <jbeulich@suse.com> wrote:

>>

>> On 11.11.2019 18:15,  H.J. Lu  wrote:

>>> On Mon, Nov 11, 2019 at 4:01 AM Jan Beulich <jbeulich@suse.com> wrote:

>>>> --- a/opcodes/i386-opc.tbl

>>>> +++ b/opcodes/i386-opc.tbl

>>>> @@ -2797,9 +2797,7 @@ pswapd, 2, 0xf0f, 0xbb, 2, Cpu3dnowA, Mo

>>>>

>>>>  // AMD extensions.

>>>>  syscall, 0, 0xf05, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

>>>> -syscall, 0, 0xf05, None, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

>>>>  sysret, 0, 0xf07, None, 2, CpuSYSCALL, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }

>>>> -sysret, 0, 0xf07, None, 2, Cpu64, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }

>>>>  swapgs, 0, 0xf01f8, None, 3, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

>>>>  rdtscp, 0, 0xf01f9, None, 3, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

>>>

>>> Can you add a testcase?

>>

>> The insns are being tested already, so I wonder what you want to be

>> tested in addition. What completely lacks testing are SYSENTER/SYSEXIT.

> 

> That is fine then.


I'll take this as an OK to the original patch then.

Thanks, Jan

Patch

--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2797,9 +2797,7 @@  pswapd, 2, 0xf0f, 0xbb, 2, Cpu3dnowA, Mo
 
 // AMD extensions.
 syscall, 0, 0xf05, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-syscall, 0, 0xf05, None, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 sysret, 0, 0xf07, None, 2, CpuSYSCALL, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
-sysret, 0, 0xf07, None, 2, Cpu64, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
 swapgs, 0, 0xf01f8, None, 3, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 rdtscp, 0, 0xf01f9, None, 3, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }