x86: bogus VMOVD with 64-bit operands should only allow for registers

Message ID 5A9FAD0F02000078001AF3E1@prv-mh.provo.novell.com
State New
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Series
  • x86: bogus VMOVD with 64-bit operands should only allow for registers
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Commit Message

Jan Beulich March 7, 2018, 8:12 a.m.
These templates exist solely to satisfy gcc's needs, and gcc only
produces these with register operands.

gas/
2018-03-07  Jan Beulich  <jbeulich@suse.com>

	* testsuite/gas/i386/x86-64-movd.s: Drop bogus vmovd memory forms.
	* testsuite/gas/i386/x86-64-movd.d,
	testsuite/gas/i386/x86-64-movd-intel.d: Adjust expectations.

opcodes/
2018-03-07  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (vmovd): Disallow Qword memory operands.
	* i386-tlb.h: Re-generate.

Comments

H.J. Lu March 7, 2018, 12:22 p.m. | #1
On Wed, Mar 7, 2018 at 12:12 AM, Jan Beulich <JBeulich@suse.com> wrote:
> These templates exist solely to satisfy gcc's needs, and gcc only

> produces these with register operands.

>

> gas/

> 2018-03-07  Jan Beulich  <jbeulich@suse.com>

>

>         * testsuite/gas/i386/x86-64-movd.s: Drop bogus vmovd memory forms.

>         * testsuite/gas/i386/x86-64-movd.d,

>         testsuite/gas/i386/x86-64-movd-intel.d: Adjust expectations.

>

> opcodes/

> 2018-03-07  Jan Beulich  <jbeulich@suse.com>

>

>         * i386-opc.tbl (vmovd): Disallow Qword memory operands.

>         * i386-tlb.h: Re-generate.

>


OK.

Thanks.

-- 
H.J.

Patch

--- a/gas/testsuite/gas/i386/x86-64-movd.d
+++ b/gas/testsuite/gas/i386/x86-64-movd.d
@@ -39,8 +39,6 @@  Disassembly of section .text:
  +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  %xmm1,0x80\(%rax\)
  +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  %xmm1,0x80\(%rax\)
  +[a-f0-9]+:	62 f1 7d 08 7e c8    	vmovd  %xmm1,%eax
- +[a-f0-9]+:	c4 e1 f9 6e 88 80 00 00 00 	vmovq  0x80\(%rax\),%xmm1
  +[a-f0-9]+:	c4 e1 f9 6e c8       	vmovq  %rax,%xmm1
- +[a-f0-9]+:	c4 e1 f9 7e 88 80 00 00 00 	vmovq  %xmm1,0x80\(%rax\)
  +[a-f0-9]+:	c4 e1 f9 7e c8       	vmovq  %xmm1,%rax
 #pass
--- a/gas/testsuite/gas/i386/x86-64-movd-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-movd-intel.d
@@ -40,8 +40,6 @@  Disassembly of section .text:
  +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
  +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
  +[a-f0-9]+:	62 f1 7d 08 7e c8    	vmovd  eax,xmm1
- +[a-f0-9]+:	c4 e1 f9 6e 88 80 00 00 00 	vmovq  xmm1,QWORD PTR \[rax\+0x80\]
  +[a-f0-9]+:	c4 e1 f9 6e c8       	vmovq  xmm1,rax
- +[a-f0-9]+:	c4 e1 f9 7e 88 80 00 00 00 	vmovq  QWORD PTR \[rax\+0x80\],xmm1
  +[a-f0-9]+:	c4 e1 f9 7e c8       	vmovq  rax,xmm1
 #pass
--- a/gas/testsuite/gas/i386/x86-64-movd.s
+++ b/gas/testsuite/gas/i386/x86-64-movd.s
@@ -35,7 +35,5 @@  _start:
 	{evex} vmovd dword ptr [rax + 128], xmm1
 	{evex} vmovd [rax + 128], xmm1
 	{evex} vmovd eax, xmm1
-	vmovd xmm1, qword ptr [rax + 128]
 	vmovd xmm1, rax
-	vmovd qword ptr [rax + 128], xmm1
 	vmovd rax, xmm1
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2058,9 +2058,9 @@  vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm
 // support assembler for AMD64, we accept 64bit operand on vmovd so
 // that we can use one template for both SSE and AVX instructions.
 vmovd, 2, 0x666e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Qword|BaseIndex, RegXMM }
+vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64, RegXMM }
 vmovd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|Reg32|BaseIndex }
-vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64|Qword|BaseIndex }
+vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64|RegMem }
 vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
 vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM }
 vmovdqa, 2, 0x666f, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }