[PATCH.,AArch64,2/2] Update Store Allocation Tag instructions.

Message ID 9b2a72a5-76d3-6dfd-7f47-a797e123bc29@arm.com
State New
Headers show
Series
  • [AArch64,1/2] Add new LDGM/STGM instruction
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Commit Message

Sudakshina Das April 2, 2019, 4:09 p.m.
Hi

On 02/04/2019 17:06, Sudakshina Das wrote:
> Hi

> 

> This patch adds the new LDGM/STGM instructions of the

> Armv8.5-A Memory Tagging Extension. This is part of the changes

> that have been introduced recently in the 00bet10 release

> https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools 

> 

> 

> The instructions are as follows:

> LDGM Xt, [<Xn|SP>]

> https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldgm-load-tag-multiple 

> 

> 

> STGM Xt, [<Xn|SP>]

> https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/stgm-store-tag-multiple 

> 

> 

> For ease of review I have not added the regenerated files in the patch. 

> I will add those in my final commit.

> 

> Builds and reg tests all pass on aarch64-none-elf.

> 

> Is this ok for trunk? And for backport to 2.32?

> 

> Thanks

> Sudi

> 

> *** gas/ChangeLog ***

> 

> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

> 

>      * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and 

> stgm.

>      * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.

>      * testsuite/gas/aarch64/illegal-memtag.l: Likewise.

>      * testsuite/gas/aarch64/illegal-memtag.s: Likewise.

> 

> *** opcodes/ChangeLog ***

> 

> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

> 

>      * aarch64-asm-2.c: Regenerated.

>      * aarch64-dis-2.c: Likewise.

>      * aarch64-opc-2.c: Likewise.

>      * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.


Hi

This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools

All of these instructions have an updated register operand (Xt -> <Xt|SP>)

- STG <Xt|SP>, [<Xn|SP>, #<simm>]
- STG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STG <Xt|SP>, [<Xn|SP>], #<simm>
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZG <Xt|SP>, [<Xn|SP>], #<simm>
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- ST2G <Xt|SP>, [<Xn|SP>], #<simm>
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZ2G <Xt|SP>, [<Xn|SP>], #<simm>

https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order

In order to accept <Rt|SP> a new operand type Rt_SP is introduced which 
has the same field as FLD_Rt but follows other semantics of Rn_SP.

For ease of review I have not added the regenerated files in the patch. 
I will add those in my final commit.

Builds and reg tests all pass on aarch64-none-elf.

Is this ok for trunk? And for backport to 2.32?

Thanks
Sudi

*** gas/ChangeLog ***

2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (process_omitted_operand): Add case for
	AARCH64_OPND_Rt_SP.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** include/ChangeLog ***

2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.

*** opcodes/ChangeLog ***

2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Add case for
	AARCH64_OPND_Rt_SP.
	(verify_constraints): Likewise.
	* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
	(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
	to accept Rt|SP as first operand.
	(AARCH64_OPERANDS): Add new Rt_SP.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

Comments

Sudakshina Das April 10, 2019, 9:36 a.m. | #1
Ping!

On 02/04/2019 17:09, Sudakshina Das wrote:
> Hi

> 

> On 02/04/2019 17:06, Sudakshina Das wrote:

>> Hi

>>

>> This patch adds the new LDGM/STGM instructions of the

>> Armv8.5-A Memory Tagging Extension. This is part of the changes

>> that have been introduced recently in the 00bet10 release

>> https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools 

>>

>>

>> The instructions are as follows:

>> LDGM Xt, [<Xn|SP>]

>> https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldgm-load-tag-multiple 

>>

>>

>> STGM Xt, [<Xn|SP>]

>> https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/stgm-store-tag-multiple 

>>

>>

>> For ease of review I have not added the regenerated files in the 

>> patch. I will add those in my final commit.

>>

>> Builds and reg tests all pass on aarch64-none-elf.

>>

>> Is this ok for trunk? And for backport to 2.32?

>>

>> Thanks

>> Sudi

>>

>> *** gas/ChangeLog ***

>>

>> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

>>

>>      * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm 

>> and stgm.

>>      * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.

>>      * testsuite/gas/aarch64/illegal-memtag.l: Likewise.

>>      * testsuite/gas/aarch64/illegal-memtag.s: Likewise.

>>

>> *** opcodes/ChangeLog ***

>>

>> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

>>

>>      * aarch64-asm-2.c: Regenerated.

>>      * aarch64-dis-2.c: Likewise.

>>      * aarch64-opc-2.c: Likewise.

>>      * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.

> 

> Hi

> 

> This patch updates the Store allocation tags instructions in

> Armv8.5-A Memory Tagging Extension. This is part of the changes

> that have been introduced recently in the 00bet10 release

> https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools 

> 

> 

> All of these instructions have an updated register operand (Xt -> <Xt|SP>)

> 

> - STG <Xt|SP>, [<Xn|SP>, #<simm>]

> - STG <Xt|SP>, [<Xn|SP>, #<simm>]!

> - STG <Xt|SP>, [<Xn|SP>], #<simm>

> - STZG <Xt|SP>, [<Xn|SP>, #<simm>]

> - STZG <Xt|SP>, [<Xn|SP>, #<simm>]!

> - STZG <Xt|SP>, [<Xn|SP>], #<simm>

> - ST2G <Xt|SP>, [<Xn|SP>, #<simm>]

> - ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!

> - ST2G <Xt|SP>, [<Xn|SP>], #<simm>

> - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]

> - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!

> - STZ2G <Xt|SP>, [<Xn|SP>], #<simm>

> 

> https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order 

> 

> 

> In order to accept <Rt|SP> a new operand type Rt_SP is introduced which 

> has the same field as FLD_Rt but follows other semantics of Rn_SP.

> 

> For ease of review I have not added the regenerated files in the patch. 

> I will add those in my final commit.

> 

> Builds and reg tests all pass on aarch64-none-elf.

> 

> Is this ok for trunk? And for backport to 2.32?

> 

> Thanks

> Sudi

> 

> *** gas/ChangeLog ***

> 

> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

> 

>      * config/tc-aarch64.c (process_omitted_operand): Add case for

>      AARCH64_OPND_Rt_SP.

>      (parse_operands): Likewise.

>      * testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.

>      * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.

>      * testsuite/gas/aarch64/illegal-memtag.l: Likewise.

>      * testsuite/gas/aarch64/illegal-memtag.s: Likewise.

> 

> *** include/ChangeLog ***

> 

> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

> 

>      * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.

> 

> *** opcodes/ChangeLog ***

> 

> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

> 

>      * aarch64-opc.c (aarch64_print_operand): Add case for

>      AARCH64_OPND_Rt_SP.

>      (verify_constraints): Likewise.

>      * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.

>      (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions

>      to accept Rt|SP as first operand.

>      (AARCH64_OPERANDS): Add new Rt_SP.

>      * aarch64-asm-2.c: Regenerated.

>      * aarch64-dis-2.c: Regenerated.

>      * aarch64-opc-2.c: Regenerated.
Nick Clifton April 10, 2019, 4:02 p.m. | #2
Hi Sudi,

> Is this ok for trunk? And for backport to 2.32?

> *** gas/ChangeLog ***

> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

> 

> 	* config/tc-aarch64.c (process_omitted_operand): Add case for

> 	AARCH64_OPND_Rt_SP.

> 	(parse_operands): Likewise.

> 	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.

> 	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.

> 	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.

> 	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

> 

> *** include/ChangeLog ***

> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

> 

> 	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.

> 

> *** opcodes/ChangeLog ***

> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

> 

> 	* aarch64-opc.c (aarch64_print_operand): Add case for

> 	AARCH64_OPND_Rt_SP.

> 	(verify_constraints): Likewise.

> 	* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.

> 	(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions

> 	to accept Rt|SP as first operand.

> 	(AARCH64_OPERANDS): Add new Rt_SP.

> 	* aarch64-asm-2.c: Regenerated.

> 	* aarch64-dis-2.c: Regenerated.

> 	* aarch64-opc-2.c: Regenerated.

> 


Approved for mainline and the 2.32 branch.  Please apply.

Cheers
  Nick
Sudakshina Das April 11, 2019, 9:24 a.m. | #3
Hi Nick

On 10/04/2019 17:02, Nick Clifton wrote:
> Hi Sudi,

> 

>> Is this ok for trunk? And for backport to 2.32?

>> *** gas/ChangeLog ***

>> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

>>

>> 	* config/tc-aarch64.c (process_omitted_operand): Add case for

>> 	AARCH64_OPND_Rt_SP.

>> 	(parse_operands): Likewise.

>> 	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.

>> 	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.

>> 	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.

>> 	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

>>

>> *** include/ChangeLog ***

>> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

>>

>> 	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.

>>

>> *** opcodes/ChangeLog ***

>> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

>>

>> 	* aarch64-opc.c (aarch64_print_operand): Add case for

>> 	AARCH64_OPND_Rt_SP.

>> 	(verify_constraints): Likewise.

>> 	* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.

>> 	(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions

>> 	to accept Rt|SP as first operand.

>> 	(AARCH64_OPERANDS): Add new Rt_SP.

>> 	* aarch64-asm-2.c: Regenerated.

>> 	* aarch64-dis-2.c: Regenerated.

>> 	* aarch64-opc-2.c: Regenerated.

>>

> 

> Approved for mainline and the 2.32 branch.  Please apply.


Thanks for the approval. I have committed both the patches on trunk and 
will wait a few days and commit to 2.32.

Sudi
> 

> Cheers

>    Nick

>

Patch

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index d04e9a195a3ac146149bd2b64151778c76c0afcd..67b50e90cede049c491ac1c5c97848d3b6e50014 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5135,6 +5135,7 @@  process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
     case AARCH64_OPND_Rm:
     case AARCH64_OPND_Rt:
     case AARCH64_OPND_Rt2:
+    case AARCH64_OPND_Rt_SP:
     case AARCH64_OPND_Rs:
     case AARCH64_OPND_Ra:
     case AARCH64_OPND_Rt_SYS:
@@ -5511,6 +5512,7 @@  parse_operands (char *str, const aarch64_opcode *opcode)
 
 	case AARCH64_OPND_Rd_SP:
 	case AARCH64_OPND_Rn_SP:
+	case AARCH64_OPND_Rt_SP:
 	case AARCH64_OPND_SVE_Rn_SP:
 	case AARCH64_OPND_Rm_SP:
 	  po_int_reg_or_fail (REG_TYPE_R_SP);
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
index 1075a12f14f4f0dcb8529efe4bdeadb8e451c1e2..37981bc14d3f567e53ee38bf547649afdb205928 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
@@ -57,64 +57,64 @@  Disassembly of section \.text:
 .*:	badf001f 	cmpp	x0, sp
 .*:	d9200800 	stg	x0, \[x0\]
 .*:	d9200b60 	stg	x0, \[x27\]
-.*:	d920081f 	stg	xzr, \[x0\]
+.*:	d920081f 	stg	sp, \[x0\]
 .*:	d93fb81b 	stg	x27, \[x0, #-80\]
 .*:	d9200c00 	stg	x0, \[x0, #0\]!
-.*:	d9200c1f 	stg	xzr, \[x0, #0\]!
+.*:	d9200c1f 	stg	sp, \[x0, #0\]!
 .*:	d920ac1b 	stg	x27, \[x0, #160\]!
 .*:	d9200400 	stg	x0, \[x0\], #0
-.*:	d920041f 	stg	xzr, \[x0\], #0
+.*:	d920041f 	stg	sp, \[x0\], #0
 .*:	d93a641b 	stg	x27, \[x0\], #-1440
 .*:	d92ffbe0 	stg	x0, \[sp, #4080\]
-.*:	d92ffbff 	stg	xzr, \[sp, #4080\]
+.*:	d92ffbff 	stg	sp, \[sp, #4080\]
 .*:	d9300bfb 	stg	x27, \[sp, #-4096\]
 .*:	d92fffe0 	stg	x0, \[sp, #4080\]!
-.*:	d93007ff 	stg	xzr, \[sp\], #-4096
+.*:	d93007ff 	stg	sp, \[sp\], #-4096
 .*:	d9600800 	stzg	x0, \[x0\]
 .*:	d9600b60 	stzg	x0, \[x27\]
-.*:	d960081f 	stzg	xzr, \[x0\]
+.*:	d960081f 	stzg	sp, \[x0\]
 .*:	d97fb81b 	stzg	x27, \[x0, #-80\]
 .*:	d9600c00 	stzg	x0, \[x0, #0\]!
-.*:	d9600c1f 	stzg	xzr, \[x0, #0\]!
+.*:	d9600c1f 	stzg	sp, \[x0, #0\]!
 .*:	d960ac1b 	stzg	x27, \[x0, #160\]!
 .*:	d9600400 	stzg	x0, \[x0\], #0
-.*:	d960041f 	stzg	xzr, \[x0\], #0
+.*:	d960041f 	stzg	sp, \[x0\], #0
 .*:	d97a641b 	stzg	x27, \[x0\], #-1440
 .*:	d96ffbe0 	stzg	x0, \[sp, #4080\]
-.*:	d96ffbff 	stzg	xzr, \[sp, #4080\]
+.*:	d96ffbff 	stzg	sp, \[sp, #4080\]
 .*:	d9700bfb 	stzg	x27, \[sp, #-4096\]
 .*:	d96fffe0 	stzg	x0, \[sp, #4080\]!
-.*:	d97007ff 	stzg	xzr, \[sp\], #-4096
+.*:	d97007ff 	stzg	sp, \[sp\], #-4096
 .*:	d9a00800 	st2g	x0, \[x0\]
 .*:	d9a00b60 	st2g	x0, \[x27\]
-.*:	d9a0081f 	st2g	xzr, \[x0\]
+.*:	d9a0081f 	st2g	sp, \[x0\]
 .*:	d9bfb81b 	st2g	x27, \[x0, #-80\]
 .*:	d9a00c00 	st2g	x0, \[x0, #0\]!
-.*:	d9a00c1f 	st2g	xzr, \[x0, #0\]!
+.*:	d9a00c1f 	st2g	sp, \[x0, #0\]!
 .*:	d9a0ac1b 	st2g	x27, \[x0, #160\]!
 .*:	d9a00400 	st2g	x0, \[x0\], #0
-.*:	d9a0041f 	st2g	xzr, \[x0\], #0
+.*:	d9a0041f 	st2g	sp, \[x0\], #0
 .*:	d9ba641b 	st2g	x27, \[x0\], #-1440
 .*:	d9affbe0 	st2g	x0, \[sp, #4080\]
-.*:	d9affbff 	st2g	xzr, \[sp, #4080\]
+.*:	d9affbff 	st2g	sp, \[sp, #4080\]
 .*:	d9b00bfb 	st2g	x27, \[sp, #-4096\]
 .*:	d9afffe0 	st2g	x0, \[sp, #4080\]!
-.*:	d9b007ff 	st2g	xzr, \[sp\], #-4096
+.*:	d9b007ff 	st2g	sp, \[sp\], #-4096
 .*:	d9e00800 	stz2g	x0, \[x0\]
 .*:	d9e00b60 	stz2g	x0, \[x27\]
-.*:	d9e0081f 	stz2g	xzr, \[x0\]
+.*:	d9e0081f 	stz2g	sp, \[x0\]
 .*:	d9ffb81b 	stz2g	x27, \[x0, #-80\]
 .*:	d9e00c00 	stz2g	x0, \[x0, #0\]!
-.*:	d9e00c1f 	stz2g	xzr, \[x0, #0\]!
+.*:	d9e00c1f 	stz2g	sp, \[x0, #0\]!
 .*:	d9e0ac1b 	stz2g	x27, \[x0, #160\]!
 .*:	d9e00400 	stz2g	x0, \[x0\], #0
-.*:	d9e0041f 	stz2g	xzr, \[x0\], #0
+.*:	d9e0041f 	stz2g	sp, \[x0\], #0
 .*:	d9fa641b 	stz2g	x27, \[x0\], #-1440
 .*:	d9effbe0 	stz2g	x0, \[sp, #4080\]
-.*:	d9effbff 	stz2g	xzr, \[sp, #4080\]
+.*:	d9effbff 	stz2g	sp, \[sp, #4080\]
 .*:	d9f00bfb 	stz2g	x27, \[sp, #-4096\]
 .*:	d9efffe0 	stz2g	x0, \[sp, #4080\]!
-.*:	d9f007ff 	stz2g	xzr, \[sp\], #-4096
+.*:	d9f007ff 	stz2g	sp, \[sp\], #-4096
 .*:	69000000 	stgp	x0, x0, \[x0\]
 .*:	69006c00 	stgp	x0, x27, \[x0\]
 .*:	6900001b 	stgp	x27, x0, \[x0\]
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
index 50c9962a40eb2fa9ca6a73f5d09efa98764576e1..bd01d73b00a0c4398f45415df74840edeb8ac4fb 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
@@ -19,19 +19,19 @@  func:
 	.macro expand_stg op
 	\op x0, [x0, #0]
 	\op x0, [x27, #0]
-	\op xzr, [x0, #0]
+	\op sp, [x0, #0]
 	\op x27, [x0, #-80]
 	\op x0, [x0, #0]!
-	\op xzr, [x0, #0]!
+	\op sp, [x0, #0]!
 	\op x27, [x0, #160]!
 	\op x0, [x0], #0
-	\op xzr, [x0], #0
+	\op sp, [x0], #0
 	\op x27, [x0], #-1440
 	\op x0, [sp, #4080]
-	\op xzr, [sp, #4080]
+	\op sp, [sp, #4080]
 	\op x27, [sp, #-4096]
 	\op x0, [sp, #4080]!
-	\op xzr, [sp], #-4096
+	\op sp, [sp], #-4096
 	.endm
 
 	.macro expand_ldg_bulk op
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
index 693410be64fdffc08e2f6df5c90950eac5f15c2f..67ec2831a52c3c14cd23b3c239a0a534cef250fd 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.l
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -38,10 +38,10 @@ 
 [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `st2g x2,\[xzr,#0\]!'
 [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzg x2,\[xzr\],#0'
 [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stz2g x2,\[xzr,#0\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stg sp,\[x2,#0\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `st2g sp,\[x2,#0\]!'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stzg sp,\[x2\],#0'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stz2g sp,\[x2,#0\]'
+[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stg xzr,\[x2,#0\]'
+[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `st2g xzr,\[x2,#0\]!'
+[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stzg xzr,\[x2\],#0'
+[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stz2g xzr,\[x2,#0\]'
 [^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
 [^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
 [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s
index 2aaabc19a1fa581fe0741abb0fc2f17b9a33f688..aa574f40f41fd10e5d138df3e38fb7512b93d764 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.s
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.s
@@ -51,10 +51,10 @@  func:
 	st2g x2, [xzr, #0]!
 	stzg x2, [xzr], #0
 	stz2g x2, [xzr, #0]
-	stg sp, [x2, #0]
-	st2g sp, [x2, #0]!
-	stzg sp, [x2], #0
-	stz2g sp, [x2, #0]
+	stg xzr, [x2, #0]
+	st2g xzr, [x2, #0]!
+	stzg xzr, [x2], #0
+	stz2g xzr, [x2, #0]
 	stgp sp, x2, [x3]
 	stgp x1, sp, [x3]
 	stgp x0, x0, [xzr]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 0c0234ab20925dbfe2e008387268bb0b335fe049..5dc5fb750a234928c7b41d771c27c8b32ac49bcb 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -184,6 +184,7 @@  enum aarch64_opnd
   AARCH64_OPND_Rm,	/* Integer register as source.  */
   AARCH64_OPND_Rt,	/* Integer register used in ld/st instructions.  */
   AARCH64_OPND_Rt2,	/* Integer register used in ld/st pair instructions.  */
+  AARCH64_OPND_Rt_SP,	/* Integer Rt or SP used in STG instructions.  */
   AARCH64_OPND_Rs,	/* Integer register used in ld/st exclusive.  */
   AARCH64_OPND_Ra,	/* Integer register used in ddp_3src instructions.  */
   AARCH64_OPND_Rt_SYS,	/* Integer register used in system instructions.  */
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a17411622cbc4b8bd29f4a8e9d5ef48029af09d1..277fa7bf84f7c95372417c6fa6c580a1b1ec0cef 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3156,6 +3156,7 @@  aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
 
     case AARCH64_OPND_Rd_SP:
     case AARCH64_OPND_Rn_SP:
+    case AARCH64_OPND_Rt_SP:
     case AARCH64_OPND_SVE_Rn_SP:
     case AARCH64_OPND_Rm_SP:
       assert (opnd->qualifier == AARCH64_OPND_QLF_W
@@ -4928,6 +4929,7 @@  verify_constraints (const struct aarch64_inst *inst,
 		  case AARCH64_OPND_Rn:
 		  case AARCH64_OPND_Rm:
 		  case AARCH64_OPND_Rn_SP:
+		  case AARCH64_OPND_Rt_SP:
 		  case AARCH64_OPND_Rm_SP:
 		    if (inst_op.reg.regno == blk_dest.reg.regno)
 		      {
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 725c86805acf2748df69dc3531d2d11182643e16..1eaccca5ec506796cd11049ba718f88127d844e7 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -125,10 +125,11 @@ 
   QLF1(X),			\
 }
 
-/* e.g. STG Xt, [<Xn|SP>, #<imm9>].  */
+/* e.g. STG <Xt|SP>, [<Xn|SP>, #<imm9>].  */
 #define QL_LDST_AT		\
 {				\
   QLF2(X, imm_tag),		\
+  QLF2(SP, imm_tag),		\
 }
 
 /* e.g. RBIT <Wd>, <Wn>.  */
@@ -3239,14 +3240,14 @@  struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
   CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
   /* Load/store Allocation Tag instructions.  */
-  MEMTAG_INSN ("stg",  0xd9200800, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
-  MEMTAG_INSN ("stzg", 0xd9600800, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
-  MEMTAG_INSN ("st2g", 0xd9a00800, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
-  MEMTAG_INSN ("stz2g",0xd9e00800, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
-  MEMTAG_INSN ("stg",  0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
-  MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
-  MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
-  MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
+  MEMTAG_INSN ("stg",  0xd9200800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
+  MEMTAG_INSN ("stzg", 0xd9600800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
+  MEMTAG_INSN ("st2g", 0xd9a00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
+  MEMTAG_INSN ("stz2g",0xd9e00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
+  MEMTAG_INSN ("stg",  0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
+  MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
+  MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
+  MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
   /* Load/store register (unsigned immediate).  */
   CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
   CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
@@ -4520,6 +4521,8 @@  struct aarch64_opcode aarch64_opcode_table[] =
     Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register")	\
     Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register")	\
     Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register")	\
+    Y(INT_REG, regno, "Rt_SP", OPD_F_MAYBE_SP, F(FLD_Rt),		\
+      "an integer or stack pointer register")				\
     Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register")	\
     Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register")	\
     X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt),	\