[AArch64,1/2] Add new LDGM/STGM instruction

Message ID 95a8c6ae-ea0e-8d0b-8db7-98c2a08c74e2@arm.com
State New
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Series
  • [AArch64,1/2] Add new LDGM/STGM instruction
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Commit Message

Sudakshina Das April 2, 2019, 4:06 p.m.
Hi

This patch adds the new LDGM/STGM instructions of the
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools

The instructions are as follows:
LDGM Xt, [<Xn|SP>]
https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldgm-load-tag-multiple

STGM Xt, [<Xn|SP>]
https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/stgm-store-tag-multiple

For ease of review I have not added the regenerated files in the patch. 
I will add those in my final commit.

Builds and reg tests all pass on aarch64-none-elf.

Is this ok for trunk? And for backport to 2.32?

Thanks
Sudi

*** gas/ChangeLog ***

2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** opcodes/ChangeLog ***

2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
	* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.

Comments

Nick Clifton April 10, 2019, 4:01 p.m. | #1
Hi Sudi,

> Is this ok for trunk? And for backport to 2.32?


> *** gas/ChangeLog ***

> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

> 

> 	* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.

> 	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.

> 	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.

> 	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

> 

> *** opcodes/ChangeLog ***

> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

> 

> 	* aarch64-asm-2.c: Regenerated.

> 	* aarch64-dis-2.c: Likewise.

> 	* aarch64-opc-2.c: Likewise.

> 	* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.


Approved for the mainline and 2.32 branch.  Please apply.

Cheers
  Nick

Patch

diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
index 53a95fb..1075a12 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
@@ -143,3 +143,15 @@  Disassembly of section \.text:
 .*:	d9200379 	stzgm	x25, \[x27\]
 .*:	d92003e0 	stzgm	x0, \[sp\]
 .*:	d920001f 	stzgm	xzr, \[x0\]
+.*:	d9e00000 	ldgm	x0, \[x0\]
+.*:	d9e0001b 	ldgm	x27, \[x0\]
+.*:	d9e00360 	ldgm	x0, \[x27\]
+.*:	d9e00379 	ldgm	x25, \[x27\]
+.*:	d9e003e0 	ldgm	x0, \[sp\]
+.*:	d9e0001f 	ldgm	xzr, \[x0\]
+.*:	d9a00000 	stgm	x0, \[x0\]
+.*:	d9a0001b 	stgm	x27, \[x0\]
+.*:	d9a00360 	stgm	x0, \[x27\]
+.*:	d9a00379 	stgm	x25, \[x27\]
+.*:	d9a003e0 	stgm	x0, \[sp\]
+.*:	d9a0001f 	stgm	xzr, \[x0\]
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
index 2ca1a68..50c9962 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
@@ -113,3 +113,5 @@  func:
 	ldg x0, [x0, #-4096]
 
 	expand_ldg_bulk stzgm
+	expand_ldg_bulk ldgm
+	expand_ldg_bulk stgm
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
index aa79aac..693410b 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.l
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -14,6 +14,10 @@ 
 [^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]'
 [^:]*:[0-9]+: Error: the optional immediate offset can only be 0 at operand 2 -- `stzgm x2,\[x3,#16\]'
 [^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `stzgm x4,\[x5,#16\]!'
+[^:]*:[0-9]+: Error: the optional immediate offset can only be 0 at operand 2 -- `ldgm x2,\[x3,#16\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldgm x4,\[x5,#16\]!'
+[^:]*:[0-9]+: Error: the optional immediate offset can only be 0 at operand 2 -- `stgm x2,\[x3,#16\]'
+[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `stgm x4,\[x5,#16\]!'
 [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
 [^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
 [^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
@@ -45,3 +49,7 @@ 
 [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]'
 [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzgm x0,\[xzr\]'
 [^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stzgm sp,\[x3\]'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldgm x0,\[xzr\]'
+[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgm sp,\[x3\]'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stgm x0,\[xzr\]'
+[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgm sp,\[x3\]'
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s
index 9c9c48b..2aaabc1 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.s
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.s
@@ -24,6 +24,12 @@  func:
 	stzgm x2, [x3, #16]
 	stzgm x4, [x5, #16]!
 
+	# LDGM/STGM
+	ldgm x2, [x3, #16]
+	ldgm x4, [x5, #16]!
+	stgm x2, [x3, #16]
+	stgm x4, [x5, #16]!
+
 	# Illegal SP/XZR registers
 	irg xzr, x2, x3
 	irg x1, xzr, x3
@@ -59,3 +65,7 @@  func:
 	# Xt == Xn with writeback should not complain
 	st2g x2, [x2, #0]!
 	stzg x2, [x2], #0
+	ldgm x0, [xzr]
+	ldgm sp, [x3]
+	stgm x0, [xzr]
+	stgm sp, [x3]
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index e0c3903..725c868 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3326,6 +3326,8 @@  struct aarch64_opcode aarch64_opcode_table[] =
   RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
   RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
   RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
+  MEMTAG_INSN ("ldgm", 0xd9e00000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0),
+  MEMTAG_INSN ("stgm", 0xd9a00000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0),
   MEMTAG_INSN ("stzgm", 0xd9200000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0),
   /* Limited Ordering Regions load/store instructions.  */
   _LOR_INSN ("ldlar",  0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL,       F_GPRSIZE_IN_Q),