[i386] : Fix PR89848, ICE: in convert_op

Message ID CAFULd4Yj0HRbS_Y6BgaKoHpGzchwh6U9AFyCD2s41YqSuKbhVQ@mail.gmail.com
State New
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Series
  • [i386] : Fix PR89848, ICE: in convert_op
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Commit Message

Uros Bizjak March 28, 2019, 7:23 p.m.
On Tue, Mar 26, 2019 at 8:05 PM Uros Bizjak <ubizjak@gmail.com> wrote:
>

> Attached patch fixes a corner case in STV pass where the shift operand

> register equals shift count register. The specialization for shift

> insns marked register as processed, but didn't process shift input

> operand, leaving an unprocessed DImode register.


There is another instance of the same problem in make_vector_copies.

2019-03-28  UroŇ° Bizjak  <ubizjak@gmail.com>

    PR target/89848
    * config/i386/i386.c (dimode_scalar_chain::make_vector_copies):
    Also process XEXP (src, 0) of a shift insn.

testsuite/ChangeLog:

2019-03-28  UroŇ° Bizjak  <ubizjak@gmail.com>

    PR target/89848
    * gcc.target/i386/pr89848.c: New test.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Committed to mainline SVN, will be backported to gcc-8 branch.

Uros.

Patch

Index: testsuite/gcc.target/i386/pr89848.c
===================================================================
--- testsuite/gcc.target/i386/pr89848.c	(nonexistent)
+++ testsuite/gcc.target/i386/pr89848.c	(revision 270003)
@@ -0,0 +1,11 @@ 
+/* PR target/89848 */
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-O2 -msse2 -mtune=pentium3m" } */
+
+long long
+foo (long long x)
+{
+  x >>= 3;
+  x <<= x;
+  return x;
+}
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c	(revision 270002)
+++ config/i386/i386.c	(revision 270003)
@@ -1901,7 +1901,10 @@ 
 		 || GET_CODE (src) == LSHIFTRT)
 		&& !CONST_INT_P (XEXP (src, 1))
 		&& reg_or_subregno (XEXP (src, 1)) == regno)
-	      XEXP (src, 1) = vreg;
+	      {
+		XEXP (src, 0) = replace_with_subreg (XEXP (src, 0), reg, reg);
+		XEXP (src, 1) = vreg;
+	      }
 	  }
 	else
 	  replace_with_subreg_in_insn (insn, reg, vreg);