RISC-V: Add FP register core file support.

Message ID 20190206182424.2868-1-jimw@sifive.com
State New
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Series
  • RISC-V: Add FP register core file support.
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Commit Message

Jim Wilson Feb. 6, 2019, 6:24 p.m.
This adds fp reg support similar to the existing general reg support.

This fixes one gdb testsuite failure
FAIL: gdb.base/gcore.exp: corefile restored system registers
which fails without the patch because fcsr was missing.  Otherwise, no
regressions with riscv64-linux native testsuite run.

	gdb/
	* riscv-linux-tdep.c (riscv_linux_fregmap): New.
	(riscv_linux_fregset): New.
	(riscv_linux_iterate_over_regset_sections): Call cb for .reg2 section.
---
 gdb/riscv-linux-tdep.c | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

-- 
2.17.1

Comments

John Baldwin Feb. 6, 2019, 6:53 p.m. | #1
On 2/6/19 10:24 AM, Jim Wilson wrote:
> This adds fp reg support similar to the existing general reg support.

> 

> This fixes one gdb testsuite failure

> FAIL: gdb.base/gcore.exp: corefile restored system registers

> which fails without the patch because fcsr was missing.  Otherwise, no

> regressions with riscv64-linux native testsuite run.


Looks good to me.

-- 
John Baldwin
Andrew Burgess Feb. 8, 2019, 10:31 a.m. | #2
* Jim Wilson <jimw@sifive.com> [2019-02-06 10:24:24 -0800]:

> This adds fp reg support similar to the existing general reg support.

> 

> This fixes one gdb testsuite failure

> FAIL: gdb.base/gcore.exp: corefile restored system registers

> which fails without the patch because fcsr was missing.  Otherwise, no

> regressions with riscv64-linux native testsuite run.

> 

> 	gdb/

> 	* riscv-linux-tdep.c (riscv_linux_fregmap): New.

> 	(riscv_linux_fregset): New.

> 	(riscv_linux_iterate_over_regset_sections): Call cb for .reg2

> 	section.


Looks good to me.

Thanks,
Andrew



> ---

>  gdb/riscv-linux-tdep.c | 23 +++++++++++++++++++++--

>  1 file changed, 21 insertions(+), 2 deletions(-)

> 

> diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c

> index e1f8e76567..91061c5b3e 100644

> --- a/gdb/riscv-linux-tdep.c

> +++ b/gdb/riscv-linux-tdep.c

> @@ -37,6 +37,16 @@ static const struct regcache_map_entry riscv_linux_gregmap[] =

>    { 0 }

>  };

>  

> +/* Define the FP register mapping.  The kernel puts the 32 FP regs first, and

> +   then FCSR.  */

> +

> +static const struct regcache_map_entry riscv_linux_fregmap[] =

> +{

> +  { 32, RISCV_FIRST_FP_REGNUM, 0 },

> +  { 1, RISCV_CSR_FCSR_REGNUM, 0 },

> +  { 0 }

> +};

> +

>  /* Define the general register regset.  */

>  

>  static const struct regset riscv_linux_gregset =

> @@ -44,6 +54,13 @@ static const struct regset riscv_linux_gregset =

>    riscv_linux_gregmap, regcache_supply_regset, regcache_collect_regset

>  };

>  

> +/* Define the FP register regset.  */

> +

> +static const struct regset riscv_linux_fregset =

> +{

> +  riscv_linux_fregmap, regcache_supply_regset, regcache_collect_regset

> +};

> +

>  /* Define hook for core file support.  */

>  

>  static void

> @@ -54,8 +71,10 @@ riscv_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,

>  {

>    cb (".reg", (32 * riscv_isa_xlen (gdbarch)), (32 * riscv_isa_xlen (gdbarch)),

>        &riscv_linux_gregset, NULL, cb_data);

> -

> -  /* TODO: Add FP register support.  */

> +  /* The kernel is adding 8 bytes for FCSR.  */

> +  cb (".reg2", (32 * riscv_isa_flen (gdbarch)) + 8,

> +      (32 * riscv_isa_flen (gdbarch)) + 8,

> +      &riscv_linux_fregset, NULL, cb_data);

>  }

>  

>  /* Signal trampoline support.  */

> -- 

> 2.17.1

>
Jim Wilson Feb. 8, 2019, 9:27 p.m. | #3
On Fri, Feb 8, 2019 at 2:31 AM Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
> * Jim Wilson <jimw@sifive.com> [2019-02-06 10:24:24 -0800]:

> >       gdb/

> >       * riscv-linux-tdep.c (riscv_linux_fregmap): New.

> >       (riscv_linux_fregset): New.

> >       (riscv_linux_iterate_over_regset_sections): Call cb for .reg2

> >       section.

>

> Looks good to me.


Thanks.  Committed.

Jim

Patch

diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c
index e1f8e76567..91061c5b3e 100644
--- a/gdb/riscv-linux-tdep.c
+++ b/gdb/riscv-linux-tdep.c
@@ -37,6 +37,16 @@  static const struct regcache_map_entry riscv_linux_gregmap[] =
   { 0 }
 };
 
+/* Define the FP register mapping.  The kernel puts the 32 FP regs first, and
+   then FCSR.  */
+
+static const struct regcache_map_entry riscv_linux_fregmap[] =
+{
+  { 32, RISCV_FIRST_FP_REGNUM, 0 },
+  { 1, RISCV_CSR_FCSR_REGNUM, 0 },
+  { 0 }
+};
+
 /* Define the general register regset.  */
 
 static const struct regset riscv_linux_gregset =
@@ -44,6 +54,13 @@  static const struct regset riscv_linux_gregset =
   riscv_linux_gregmap, regcache_supply_regset, regcache_collect_regset
 };
 
+/* Define the FP register regset.  */
+
+static const struct regset riscv_linux_fregset =
+{
+  riscv_linux_fregmap, regcache_supply_regset, regcache_collect_regset
+};
+
 /* Define hook for core file support.  */
 
 static void
@@ -54,8 +71,10 @@  riscv_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
 {
   cb (".reg", (32 * riscv_isa_xlen (gdbarch)), (32 * riscv_isa_xlen (gdbarch)),
       &riscv_linux_gregset, NULL, cb_data);
-
-  /* TODO: Add FP register support.  */
+  /* The kernel is adding 8 bytes for FCSR.  */
+  cb (".reg2", (32 * riscv_isa_flen (gdbarch)) + 8,
+      (32 * riscv_isa_flen (gdbarch)) + 8,
+      &riscv_linux_fregset, NULL, cb_data);
 }
 
 /* Signal trampoline support.  */